Controlled delay‐through dynamic logic: leakage‐tolerant high‐speed dynamic logic

Abstract

A new model for dynamic logic is proposed with low power consumption and leakage without the degradation of speed. This logic works perfectly with cascaded and differential style without inverters. Controlled delay-through dynamic logic (CDTDL) is comparatively faster than other dynamic logics because of the parallel-type configuration with clock and inputs. CDTDL-based circuits can perform better in high-frequency operations due to lower propagation delay and dynamic power consumption at the cost of area. The proposed technique can avoid the chance of leakage current with the help of a control block and a delayed clock mechanism. The simulation results show that the new dynamic logic using 180 nm technology yields a minimum 49.7% improvement in power delay product compared with its predecessors such as conventional domino and current comparison-based domino for standard circuits.