An efficient design technique for low power dynamic feedthrough logic with enhanced performance for wide fan-in gates

Abstract

This paper presents a new approach to high performance and low power circuit for wide fan-in gates using a new CMOS logic known as feedthrough logic (FTL). Feedthrough logic can improve the performance by partial evaluation in its computational block before getting a valid input. The FTL is more suited for those circuits which consists of a critical path of large cascaded inverting gates. FTL based circuits can perform better in both high fan-out and high frequency operations due to both dynamic power consumption and lower delay at the cost of area. The proposed circuit achieves a reduction in the average power. The comparison analysis has been carried out by simulating the logic circuit by 180 nm technology. The proposed modified FTL reduces total power consumption up to 13.25% in wide fan-in NAND gates and 99.9% in wide fan-in NOR gates. This model works more effectively in the case of NOR gates but creates more delay as compared to other proposed FTL models.