A new design technique for low power dynamic feedthrough logic with delay element

Abstract

This paper presents a new approach for high performance and low power circuit using a new CMOS logic known as feedthrough logic (FTL). Feedthrough logic can improve the performance by partial evaluation in its computational block before getting a valid input. The FTL is more suited for those circuits which consist of a critical path of large cascaded inverting gates. FTL based circuit can perform better in both high fan out and high frequency operations due to both lesser delay and dynamic power consumption at the cost of area. A 2 bit conventional multiplier circuit with proposed model is simulated. The proposed circuit achieves a reduction in the average power and delay. The comparison analysis has been simulated by 180 nm CMOS technology. The proposed modified FTL reduces total power delay product up to 22.85% in NAND gates and 11.63% in NOR gates. The results of 2 bit multiplier simulation also confirms that the proposed model can perform with better as compared with existing models of FTL with less transistor count.