Fast adder design in dynamic logic

Abstract

This paper presents the design of fast adder structures using a new CMOS logic family - feedthrough logic (FTL). The FTL is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, FTL based circuits perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low power FTL provides for smaller propagation time delay (4.1 times), lower energy consumption (30.1%), and similar combined delay, power consumption and active area product (0.9% worst).