Design impacts of delay invariant high‐speed clock delayed dual keeper domino circuit

Abstract

Precise keeper control of domino logic circuit can significantly increase the speed of operation. However, the positive feedback gain associated with the feedback keeper circuit unduly increases the delay variability. Here, a novel high-speed clock delayed dual keeper (CDDK) domino circuit is presented, which aims at reducing the delay and lower the impact of loop gain on delay variability. In CDDK domino structure, the keeper circuit comprising of two keeper devices is disabled during the initial evaluation phase. This significantly reduces the contention current and thereby the operating speed of the circuit is enhanced. The simulations of the circuits have been carried out for various metrics and the results have been analysed. Furthermore, the Monte-Carlo simulations carried out for 2000 runs on a 128-input OR gate using CDDK structure demonstrate reduced delay variability characteristics due to smaller loop gain of the CDDK domino structure against the conventional domino logic style. The enhanced speed of operation due to reduced contention current is demonstrated. The results are validated through comparison against the conventional domino logic counterpart circuits. The analyses of the circuits are performed using industry standard full-suite Cadence® tools using 90 nm technology library.