Conventional Complementary Metal Oxide Semiconductor Research Articles

A comparative study on the effects of technology nodes and logic styles for low power high speed VLSI applications

Carbon nanotubes (CNT) field-effect transistor (CNTFET) could be a possible alternative to CMOS technology for future VLSI applications. In this work, a comparative study has been carried out on the effects of technology nodes and logic styles on power dissipation, delay, leakages, etc. The technology nodes that are considered here are 90 nm and 32 nm MOSFET technology, and 32 nm CNTFET technology. The logic families considered here are the conventional complementary metal-oxide-semiconductor (CMOS), complementary pass transistor logic (CPL) and transmission gate (TG). The digital circuits considered are NAND, NOR, XOR and MUX gates. HSPICE simulations have been carried out and observed that at 32 nm CNTFET technology, the least power, worst-case delay and least PDP are found as 15.5 nW, 3.11 ps and 0.048 aJ, respectively. It is witnessed that CNTFET-based logics are superior compared to other logic families at different technology nodes.

From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review

Spintronics is one of the growing research areas which has the capability to overcome the issues of static power dissipation and volatility suffered by the complementary metal-oxide-semiconductor (CMOS) industry. Magnetic tunnel junction (MTJ), one of the prominent spintronic devices, is not only used to develop the fully non-volatile-logic (NV-L) but combines magnetism and electronics to develop next-generation NV-memory (NV-M) and hybrid CMOS/MTJ circuits. To be specific towards hybrid CMOS/MTJ circuits, the fabrication of first hybrid full-adder in 2009, fabrication of MTJ based 240-tile NV-field programmable gate array (NV-FPGA) chip in 2013, fabrication of a 3000-6-input-LUTs based NV-FPGA chip in 2015, fabrication of MTJ based NV-logic-in-memory-large scale integration (NV-LIM-LSI) in 2017 and recently the fabrication of a full hybrid magnetic/CMOS System on Chip (SoC) under EU GREAT Project in 2019 has strengthened the belief and motivated the researcher to be continued in this domain. This review article aims to provide the complete design flow of hybrid CMOS/MTJ circuits developed using one of the fab compatible MTJ spintronic devices and its integration with conventional CMOS logic. The broad coverage of the article is MTJ construction, its switching mechanisms, a brief history of various compact models, reliability issues, and the concept of logic-in-memory (LIM) architecture. Finally, the article concludes with the challenges and future prospects of hybrid CMOS/MTJ circuits, which will motivate people in academia to cultivate research in this domain and industry to realize the prototype for a wide range of potential applications.

Implementation of VLSI Architecture for Montgomery Modular Multiplier

The paper proposes a Montgomery Modular Multiplier (MMM) using a simple and efficient Montgomery multiplication algorithm. Here a modification in the form of using hybrid full adders in the Carry Save adder is proposed. The hybrid full adder is designed using a conventional Complementary Metal Oxide Semiconductor and transmission gate logic. There is about 54% and 55% reduction of area (no. of components) in Radix 2 MMM and Semi-Carry-Save (SCS) based MMM with hybrid full adders. There is significant reduction in the power dissipation of 52% for Radix 2 MMM and 46% of SCS based MMM when hybrid adders are used instead of C-CMOS Full-Adders. The delay is also reduced by 47% in SCS based MMM as compared to that of Radix 2 MMM. The software used are Xilinx ISE 14.2 and Mentor Graphics Pyxis Schematic in 180-nm technology.

The Mixed Logic Style based Low Power and High Speed One-bit Binary adder for SOI designs AT 32NM Technology

Binary adders are the fundamental building blocks to construct Data Processing arithmetic units. A novel one-bit full adder is presented in this paper which is designed by Mixed logic design style. In addition to small size transistors and reduced transistor activity compared to conventional CMOS (Complementary Metal Oxide Semiconductor) gates, it provides the priority between the High logic and Low logic for the computation of the output. Various logic topologies are used to design the one-bit full adder like High-Skew(Hi-Skew), Low-Skew(Li-Skew), TGL (Transmission Gate Logic) and DVL (Dual Voltage Logic). This new approach gives the better operating speed, low power consumption compared to conventional logic design by reducing the transistors activity and by improving the driving capability. This Mixed logic style provides 83.53% average power consumption and Propagation Delay of 14.02% at 0.8v. The H-SPICE simulation tool is used for construction and evaluation of the Full adder logic at different voltages. The 32nm model file is used for MOS transistors.

An Optimized Counter Design using T Flip-Flop in Quantum-Dot Cellular Automata Technology

Conventional CMOS technology have lot of limitations and serious challenges threat this technology when scaled to a nano-level. Several alternative technologies have been proposed as solutions to overcome limitations and challenges encountered by CMOS. Quantum dot-cellular automata (QCA) is an emerging nanotechnology for the development of logic circuits such as combinational and sequential circuits.QCA seems to be best alternative to the conventional complementary metal-oxide semiconductor (CMOS) technology.QCA is a new computing paradigm in nanotechnology that can implement digital circuits with outstanding features such as ultralow power consumption, faster switching speed and extremely density structure . In this paper , a novel area efficient and optimized QCA layout design of sequential circuit T flip flop is proposed by which the QCA layout area has reduced by 57% , cell count improved by 56% in comparison with the earlier best designs. The use of proposed T flip flop in designing sequential circuits like synchronous 2 bit up counter,3 bit up counter and 4 bit up counter has reduced the QCA layout area by 65%,64% and 68% respectively where as QCA cell count are reduced by 53%, 62% and 59%.. The sequential circuits flip flop and counters are designed using three input XOR gate and are implemented by QCA layout. The paper also present the use of proposed T flip flop designed with 3 input XOR gate in designing not only synchronous binary up counters but also in synchronous binary down counter provides a significant reduction in the hardware and complexity than the existing methods. These circuits are simulated using computer aided design tool QCA Designer 2.0.3, which is a design and simulation tool for quantum dot cellular automata. The aim is to maximize the circuit density and focus on a QCA layout that uses minimal number of cells

The Mixed Logic Style based Low Power and High Speed 3-2 Compressor for ASIC designs at 32nm Technology

Compressors are the fundamental building blocks to construct Data Processing arithmetic units. A novel 3-2 Compressor is presented in this paper which is designed by Mixed logic design style. In addition to small size transistors and reduced transistor activity compared to conventional CMOS (Complementary Metal Oxide Semiconductor) gates, it provides the priority between the High logic and Low logic for the computation of the output. Various logic topologies are used to design the 3-2 compressor like High-Skew(Hi-Skew), Low-Skew(Li-Skew), TGL (Transmission Gate Logic) and DVL (Dual value Logic). This new approach gives the better operating speed, low power consumption compared to conventional logic design by reducing the transistors activity, improving the driving capability and reduced input capacitance with skew gates. Especially the Mixed logic style-3 provides 92.39% average power consumption and Propagation Delay of 99.59% at 0.8v. The H-SPICE simulation tool is used for construction and evaluation of compressor logic at different voltages. 32nm model file is used for MOS transistors

Joule-Heated and Suspended Silicon Nanowire Based Sensor for Low-Power and Stable Hydrogen Detection.

We developed self-heated, suspended, and palladium-decorated silicon nanowires (Pd-SiNWs) for high-performance hydrogen (H2) gas sensing with low power consumption and high stability against diverse environmental noises. To prepare the Pd-SiNWs, SiNWs were fabricated by conventional complementary metal-oxide-semiconductor (CMOS) processes, and Pd nanoparticles were coated on the SiNWs by a physical vapor deposition method. Suspended Pd-SiNWs were simply obtained by etching buried oxide layer and Pd deposition. Joule heating of Pd-SiNW (<1 mW) enables the detection of H2 gas with a faster response and without the reduction of sensitivity unlike other Pd-based H2 gas sensors. We proposed a H2 sensing model using oxygen adsorption on the Pd nanoparticle-coated silicon oxide surface to understand the H2 response of Joule-heated Pd-SiNWs. A suspended Pd-SiNW showed a similar transient sensing response with around four times lower Joule heating power (147 μW) than the substrate-bound Pd-SiNW (613 μW). The effect of interfering gas on the Pd-SiNW was investigated, and it was found that the Joule heating of Pd-SiNW helps to maintain the H2 sensing performance in humid or carbon monoxide environments.

An Area and Energy Efficient RAM Cell Design in Quantum Dot Cellular Automata

The Conventional Complementary Metal oxide semiconductor (CMOS) technology has been revolutionized from the past few decades. However, the CMOS circuit faces serious constraints like short channel effects, quantum effects, doping fluctuations at the nanoscale which limits them to further scaling down at nano meter range. Among various existing nanotechnologies, Quantum dot Cellular Automata (QCA) provides new solution at nanocircuit design. The technical advancement of the paper lies in designing a high performance RAM cell with less QCA cells, less occupational area and lower power dissipation characteristics. The design occupies 12.5% lower area, 16.6% lower input to output delay, and dissipates 18.26% lesser energy than the designs in the literature. The proposed RAMcell is robust due to lesser noise variations. Also it has less fabrication cost due to absence of rotated cells.

Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation

A novel design of a hybrid Full Adder (FA) using Pass Transistors (PTs), Transmission Gates (TGs) and Conventional Complementary Metal Oxide Semiconductor (CCMOS) logic is presented. Performance analysis of the circuit has been conducted using Cadence toolset. For comparative analysis, the performance parameters have been compared with twenty existing FA circuits. The proposed FA has also been extended up to a word length of 64 bits in order to test its scalability. Only the proposed FA and five of the existing designs have the ability to operate without utilizing buffer in intermediate stages while extended to 64 bits. According to simulation results, the proposed design demonstrates notable performance in power consumption and delay which accounted for low power delay product. Based on the simulation results, it can be stated that the proposed hybrid FA circuit is an attractive alternative in the data path design of modern high-speed Central Processing Units.

Enhanced performance of double gate junctionless field effect transistor by employing rectangular core–shell architecture

This paper proposes a p-type double gate junctionless field effect transistor having opposite doping in the core with that of the silicon body referring to rectangular core–shell (RCS) architecture. The use of RCS has significantly reduced the gate induced drain leakage and therefore, obtaining improved performance parameters. It is observed that the parasitic BJT action gets diminished in RCS architecture due to enlargement of tunneling width at the channel/drain interface. Further, after validating our simulations with the experimental results of junctionless p-type FET we demonstrated that insertion of oppositely doped core in silicon body helps to achieve volume depletion in OFF state. The simulation results show that junctionless FET with RCS architecture exhibit lower OFF current, higher ON/OFF ratio, better drain induced barrier lowering (DIBL) and superior subthreshold slope (SS) at lesser channel lengths. The measured values of OFF current, ON current, ON/OFF ratio, DIBL and SS at channel length 20 nm for RCS architecture are −9.96 × 10−15 A, −2.33 × 10−5 A, 0.23 × 1010, 42.1 mV V−1 and 67.7 mV/decade respectively. Interestingly, we have found a correlation between RCS thickness and channel length. Finally, a complementary metal oxide semiconductor (CMOS) inverter with RCS architecture is also designed. The voltage transfer characteristics of RCS based CMOS has been significantly improved as compared to the conventional junctionless CMOS inverter.

Nonvolatile, Spin-Based, and Low-Power Inexact Full Adder Circuits for Computing-in-Memory Image Processing

Deep submicron conventional complementary metal oxide semiconductor (CMOS) technology is facing various issues such as high static power consumption due to the increasing leakage currents. In recent years, spin-based technologies like magnetic tunnel junctions (MTJ) have emerged and shown some fascinating features to overcome the aforesaid issues of CMOS technology. The hybrid MTJ/CMOS circuits offer low power consumption, nonvolatility, and high performance. This paper proposes two novel hybrid MTJ/CMOS approximate full-adder circuits (AXMA) for low power approximate computing-in-memory architectures. The proposed AXMAs offer low area, high sensing speed, considerable lower energy consumption, and the lowest power delay product (PDP) than the considered antecedent counterparts. The proposed AXMAs also introduce the advantage of full nonvolatility to the systems. This feature allows the system to be powered off during the idle modes in order to reduce the static power without the need for any retention parts or loss of data. Applications of the proposed AXMAs in digital image processing and their effect on the quality of images considering some relevant metrics like peak signal-to-noise ratio (PSNR) and mean structural similarity (MSSIM) are also investigated using the MATLAB software.

A Novel Slice-Based High-Performance ALU Design Using Prospective Single Electron Transistor

The arithmetic logic unit (ALU) is one of the most essential components of any microprocessor or computing system that is capable of performing several arithmetic as well as logic operations. For realizing efficient and high-performance ALU, proper designing, optimum selection of materials and incorporation of advanced devices are utmost important. The single electron transistor (SET) is a prominent advanced device structure for achieving high-end computing system. In this paper, the prospective SET-based ALU is realized to meet next-generation requirements like higher speed, lower power, and volume. Also, the enhancement capability of ALU can be further accomplished by incorporating effective modular design using slice-based approach. The slice-based design approach provides simplicity and extensibility of the design. In this, each slice has the capability to perform arithmetic and logical operations on one-bit input data. Henceforth, cascading of n such slices generates the n-bit ALU. The multiplication operation is executed separately. The incorporation of separate multiplier block aids in achieving fast execution of multiplication operation with a single instruction. The performance of high-end proposed SET-based ALU is compared with the conventional complementary metal oxide semiconductor (CMOS) and 18 nm FinFET technology-based ALU designs. It is observed that the SET-based ALU gives 1.9× lesser delay and 19.8× lower power dissipation as compared to its 16 nm CMOS counterpart. Also, with respect to 18 nm FinFET-based technology, proposed SET-based design out-stands extensively in terms of lower transistor count and power.

Prototyping of an All-pMOS-Based Cross-Coupled Voltage Multiplier in Single-Well CMOS Technology for Energy Harvesting Utilizing a Gastric Acid Battery

A gastric acid battery and its charge storage in a capacitor are a simple and safe method to provide a power source to an ingestible device. For that method, the electromotive force of the battery should be boosted for storing a large amount of energy. In this study, we have proposed an all-p-channel metal-oxide semiconductor (pMOS)-based cross-coupled voltage multiplier (CCVM) utilizing single-well CMOS technology to achieve a voltage boosting higher than from a conventional complementary MOS (CMOS) CCVM. We prototyped a custom integrated circuit (IC) implemented with the above CCVMs and a ring oscillator as a clock source. The characterization experiment demonstrated that our proposed pMOS-based CCVM can boost the input voltage higher because it avoids the body effect problem resulting from an n-channel MOS transistor. This circuit was also demonstrated to significantly reduce the circuit area on the IC, which is advantageous as it reduces the chip size or provides an area for other functional circuits. This simple circuit structure based on mature and low-cost technologies matches well with disposal applications such as an ingestible device. We believe that this pMOS-based CCVM has the potential to become a useful energy harvesting circuit for ingestible devices.

Resistive random-access memory with an a-Si/SiNx double-layer

Resistive random-access memory (RRAM) with a Ni/SiNx/a-Si/p+-Si structure is presented. In contrast to RRAM devices based on high-k materials, the proposed Si-based device is more attractive and promising because the SiNx and a-Si layers have full compatibility with conventional complementary metal-oxidesemiconductor technology. The proposed device is compared to a control device with a single layer of SiNx. A conduction path containing Si dangling bonds (traps) can be generated in both the SiNx and a-Si layers. The conduction path in each layer can be controlled by the compliance current during the forming process. For high compliance current mode, the double-layer device has a higher ON/OFF ratio (∼104) and lower leakage current (∼10-9 A) than the single-layer device. For low compliance current mode, better non-linearity (∼103) can be obtained when a 1/2 read bias scheme is applied to the cross-point array.

Introducing Galois field polynomial addition in quantum-dot cellular automata

The quantum-dot cellular automata, which provides a novel nano-computation paradigm, has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor technology. This work mitigates the gap between QCA and coding theory, particularly finite field addition through a redesign-able, reproducible and scalable modular based approach. Primarily, a module to perform modulo-2 addition, namely M2A module is introduced. The notion of M2A module further results in a novel algorithm that generates an approach of QCA design of Galois field (GF)-based polynomial adders. The cost functions are calculated to estimate the operation of M2A-based polynomial adders, the proposed adders are compared with the conventional counterpart, and the best one is reported. The defect- and fault-tolerant behavior of GF(28) polynomial adder is also examined as a particular instance.

Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs

As an emerging nonvolatile device, ferroelectric field-effect transistors (FeFETs) have the potential to reduce the power and area by integrating nonvolatile storage elements with logic. The hysteretic behavior allows an FeFET to function as both a nonvolatile storage element and a switch. This paper exploits this feature of FeFETs to design lookup tables (LUTs) and routing switches, which have obvious utility in field-programmable gate arrays (FPGAs). Read and write schemes are also designed for the proposed LUTs and routing switches. Evaluation results based on a calibrated FeFET model show that the proposed designs are competitive in power and performance. For example, compared with conventional complementary metal–oxide–semiconductor (CMOS)-based equivalents, the proposed FeFET-based LUTs and routing elements improve the power-delay product (PDP) by 5.8– $16\times $ , respectively, while compared with resistive random-access memory (RRAM)-based equivalents, the proposed designs improve the PDP by 1.14– $1.8\times $ . The area of an FeFET-based FPGA is 8% smaller than a conventional CMOS-based FPGA.

Highly Selective CMOS-Compatible Mid-Infrared Thermal Emitter/Detector Slab Design Using Optical Tamm-States.

In this work, we propose and evaluate a concept for a selective thermal emitter based on Tamm plasmons suitable for monolithic on-chip integration and fabrication by conventional complementary metal oxide semiconductor (CMOS)-compatible processes. The original design of Tamm plasmon structures features a purely one-dimensional array of layers including a Bragg mirror and a metal. The resonant field enhancement next to the metal interface corresponding to optical Tamm states leads to resonant emission at the target wavelength, which depends on the lateral dimensions of the bandgap structure. We demonstrate the application of this concept to a silicon slab structure instead of deploying extended one dimensional layers thus enabling coupling into slab waveguides. Here we focus on the mid-infrared region for absorption sensing applications, particularly on the CO2 absorption line at 4.26 µm as an example. The proposed genetic-algorithm optimization process utilizing the finite-element method and the transfer-matrix method reveals resonant absorption in case of incident modes guided by the slab and, by Kirchhoff’s law, corresponds to emittance up to 90% depending on different choices of the silicon slab height when the structure is used as a thermal emitter. Although we focus on the application as an emitter in the present work, the structure can also be operated as an absorber providing adjusted lateral dimensions and/or exchanged materials (e.g., a different choice for metal).

New efficient designs of reversible logic gates and circuits in the QCA technology

Quantum-dot cellular automata (QCA) is a developing nanotechnology, which seems to be a good candidate to replace the conventional complementary metal-oxide-semiconductor (CMOS) technology. The QCA has the advantages of very low power dissipation, faster switching speed, and extremely low circuit area, which can be used in designing nanoscale reversible circuits. In this paper, the new efficient QCA implementations of the basic reversible Gates such as: CNOT, Toffoli, Feynman, Double Feynman, Fredkin, Peres, MCL, and R Gates are presented based on the straight interactions between the QCA cells. Also, the designs of 4-Bit reversible parity checker and 3-bit reversible binary to Grey converter are introduced using these optimized reversible Gates. The proposed layouts are designed and simulated using QCADesigner software. In comparison with previous QCA designs, the proposed layouts are implemented with the minimum area, minimum number of cells, and minimum delay without any wire-crossing techniques. Also, in comparison with the CMOS technology, the proposed layouts are more efficient in terms of the area and power. Therefore, our designs can be used to realize quantum computation in ultralow power computer communication.

Negative Capacitance Transistors

In recent years, the negative capacitance effect in ferroelectric (FE) materials has attracted significant attention from many researchers around the world. The negative capacitance effect promises to reduce the voltage requirement in conventional complementary metal–oxide–semiconductor transistors below what is otherwise believed to be the Boltzmann limit. In this paper, our objective is to discuss the fundamental underpinning of the negative capacitance effect and describe how it can be utilized for transistors. We shall start with a thermodynamic perspective to understand where the reduction in energy dissipation comes from. We then proceed to derive the S curve in an FE material from fundamental principles. The central result of this paper is to associate the negative slope region in the S curve to a physically definable configuration of dipoles in the crystal structure. The design of a negative capacitance transistor is essentially an exercise of stabilizing the FE in the negative slope region of the S curve using the semiconductor capacitance as a series capacitor.

Fully Nonvolatile and Low Power Full Adder Based on Spin Transfer Torque Magnetic Tunnel Junction With Spin-Hall Effect Assistance

As technology node scales down below 90 nm, the conventional complementary metal oxide semiconductor (CMOS) logic circuits suffer from various problems such as high standby power due to increase in leakage current. Spintronic devices based on magnetic tunnel junction (MTJ) is one of the most promising technology candidates for the future of the digital circuits. MTJ-based logic circuits can offer nonvolatility, high endurance, high density, low standby power dissipation, and 3-D integration capability with the CMOS technology. In recent years, several full-adder circuits are proposed based on MTJs that are not fully nonvolatile since they use MTJs to store only one of their inputs. This paper proposes a fully nonvolatile magnetic full-adder (MFA) circuit offering the capability of power gating with no loss of data. The proposed circuit stores all the inputs in MTJs using the spin-transfer torque (STT) method assisted by the spin-Hall effect (SHE). Thanks to the SHE assistance, delay and power consumption of the MTJ switching are reduced significantly. Moreover, as a result of lower write current, the endurance of the oxide barrier can be increased. Using a three-terminal SHE–STT–MTJ model and a 45 nm CMOS SPICE model, we simulated and validated the functionality of our design and compared it with some recent previous MFAs. Simulation results reveal that the proposed MFA offers considerable superiorities over the recent counterparts.