Conventional Complementary Metal Oxide Semiconductor Research Articles

A Novel One SWS-FET Transistor for AND/OR Logic Gate

This paper presents the design and modeling of AND/OR logic gate using one high-mobility n-channel spatial wave-function switched field-effect transistor (n-SWS-FET), which provide a significant reduction of cell area and power dissipation. In SWSFET, the channel between source and drain has two or more quantum well (QW) layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the two quantum well layers and it causes the switching of charge carriers from one channel to other channel of the SWS device. This switching property promises to build AND/OR logic gate with one n-SWS-FET transistor, where Complementary Metal Oxide Semiconductor (CMOS) AND/OR gate is built by 6 transistors. The proposed gate configures as AND/OR by change sources signal. The SWS-FET device with two well Si/Si0.5Ge0.5 has been modeled using Berkeley Short-channel IGFET Model (BSIM4.6.0) and Analog Behavioral Model (ABM), the model is suitable for transient analysis at circuit level. This model is optimized for AND/OR logic and used to replace a conventional CMOS logic.

Quantum-Dot Cellular Automata in Designing the Arithmetic and Logic Unit: Systematic Literature Review, Classification and Current Trends

Quantum-dot Cellular Automata (QCA) presents a new model at Nano-scale for possible substitution of conventional Complementary Metal–Oxide–Semiconductor (CMOS) technology. On the other hand, an Arithmetic Logic Unit (ALU) is a digital electronic circuit which performs arithmetic and bitwise logical operations on integer binary numbers. Therefore, QCA-based ALU is an important part of the processor in order to develop a full capability processor. Although the QCA has become very important, there is not any comprehensive and systematic work on studying and analyzing its important techniques in the field of ALU design. This paper provides the comprehensive, systematic and detailed study and survey of the state-of-the-art techniques and mechanisms in the field of QCA-based ALU designing. There are three categories in which QCA plays a role: ALU, logic unit (LU) and arithmetic unit (AU). Each category presents the important studies. In addition, this paper reviews the major developments in these three categories and it plans the new challenges. Furthermore, it provides the identification of open issues and guidelines for future research. Also, a Systematic Literature Review (SLR) on QCA-based ALU, LU and AU is discussed in this paper. We identified 1,960 papers, which are reduced to 26 primary studies through our paper selection process. According to the obtained results from 2001 to 2015, the number of published articles are very high in 2014 and low in 2005 and 2009. This survey paper also provides a discussion of considered mechanisms in terms of ALU, LU and AU attribute as well as directions for future research.

Dual‐edge triggered JK flip‐flop with comprehensive analysis in quantum‐dot cellular automata

Quantum-dot cellular automata (QCA), a new computing paradigm at nanoscale, may be a prospective substitution of conventional complementary metal oxide semiconductor (CMOS)-based integrated circuits. A new dual-edge triggered JK flip-flop based on a novel dual-edge triggered structure with less fundamental building gates is proposed in QCA domain in this study. To get a more robust triggered structure, the probabilistic transfer matrix is employed to analyse the reliability of the structure. The functionalities of the dual-edge triggered structure and JK flip-flop are verified with QCADesigner, a simulation tool widely used. By arranging the clock zones serially and QCA cells logically, compared with previous circuits, both of the proposed triggered structure and JK flip-flop perform well in terms of cells count, area, complexity, QCA cost and power dissipation at different tunnelling energy levels at 2 K temperature, respectively.

Silicon nanowire CMOS NOR logic gates featuring one-volt operation on bendable substrates

In this study, we propose complementary metal-oxide−semiconductor (CMOS) NOR logic gates consisting of silicon nanowire (NW) arrays on bendable substrates. A circuit consisting of two p-channel NW field-effect transistors (NWFETs) in series and two n-channel NWFETs in parallel is constructed to operate a two-input CMOS NOR logic gate. The NOR logic gates operate at a low supply voltage of 1 V with a rail-to-rail logic swing and a high voltage gain of approximately −3.0. The exact NOR logic functionality is achieved owing to the superior electrical characteristics of the well-aligned p- and n-NWFETs, which are obtained using conventional Si-based CMOS technology. Moreover, the NOR logic gates exhibit stable characteristics and have good mechanical properties. The proposed bendable NW CMOS NOR logic gates are promising building blocks for future bendable integrated electronics.

Multivalued static random access memory using multivalued FET

ABSTRACTQuaternary logic is very promising logic for multivalued logic implementation. Four state or quaternary static random access memory (SRAM) can be designed using quantum dot gate-quantum dot channel field effect transistor (QDG-QDCFEFT). The presence of quantum dots in the channel region as well as in the gate region of the QDG-QDCFET produces four states in its transfer characteristics. The implementation of quaternary SRAM using QDG-QDCFFET following conventional complementary metal oxide semiconductor field effect transistor architecture is for the first time presented in this paper.

Design and simulation of electro-thermal compliant MEMS logic gates

PurposeThe purpose of this paper is to design an out-of-plane micro electro-thermal-compliant actuator based logic gates which work analogously to complementary metal oxide semiconductor (CMOS) based logic gates. The proposed logic gates used a single-bit mechanical micro ETC actuator per logic instead of using 6-14 individual transistors as in CMOS.Design/methodology/approachA complete analytical modelling is performed on a single ETC vertical actuator, and a relation between the applied voltage and the out-of-plane deflection is derived. Its coupled electro-thermo-mechanical analysis is carried out using micro electro mechanical system (MEMS) CAD tool CoventorWare to illustrate its performance.FindingsThis paper reports analytical and numerical simulation of basic MEMS ETC actuator-based logic gates. The proposed logic gate operates on 5 V, which suits well with conventional CMOS logic, which in turn reduces the power consumption of the device.Originality/valueThe proposed logic gates uses a single-bit MEMS ETC actuator per logic instead of using more transistors as in CMOS. The unique feature of this proposed logic gates is that the basic mechanical ETC actuator is customized in its structure to function as specific logic gates depending upon the given inputs.

Electrical characteristics of silicon nanowire CMOS inverters under illumination

In this study, we examine the electrical characteristics of complementary metal-oxide-semiconductor (CMOS) inverters with silicon nanowire (SiNW) channels on transparent substrates under illumination. The electrical characteristics vary with the wavelength and power of light due to the variation in the generation rates of the electric-hole pairs. Compared to conventional optoelectronic devices that sense the on/off states by the variation in the current, our device achieves the sensing of the on/off states with more precision by using the voltage variation induced by the wavelength or intensity of light. The device was fabricated on transparent substrates to maximize the light absorption using conventional CMOS technologies. The key difference between our SiNW CMOS inverters and conventional optoelectronic devices is the ability to control the flow of charge carriers more effectively. The improved sensitivity accomplished with the use of SiNW CMOS inverters allows better control of the on/off states.

A Real-Time Ultraviolet Radiation Imaging System Using an Organic Photoconductive Image Sensor.

We have developed a real time ultraviolet (UV) imaging system that can visualize both invisible UV light and a visible (VIS) background scene in an outdoor environment. As a UV/VIS image sensor, an organic photoconductive film (OPF) imager is employed. The OPF has an intrinsically higher sensitivity in the UV wavelength region than those of conventional consumer Complementary Metal Oxide Semiconductor (CMOS) image sensors (CIS) or Charge Coupled Devices (CCD). As particular examples, imaging of hydrogen flame and of corona discharge is demonstrated. UV images overlapped on background scenes are simply made by on-board background subtraction. The system is capable of imaging weaker UV signals by four orders of magnitude than that of VIS background. It is applicable not only to future hydrogen supply stations but also to other UV/VIS monitor systems requiring UV sensitivity under strong visible radiation environment such as power supply substations.

Survey of Photonic and Plasmonic Interconnect Technologies for Intra-Datacenter and High-Performance Computing Communications

Large scale data centers (DC) and high performance computing (HPC) systems require more and more computing power at higher energy efficiency. They are already consuming megawatts of power, and a linear extrapolation of trends reveals that they may eventually lead to unrealistic power consumption scenarios in order to satisfy future requirements (e.g., Exascale computing). Conventional complementary metal oxide semiconductor (CMOS)-based electronic interconnects are not expected to keep up with the envisioned future board-to-board and chip-to-chip (within multi-chip-modules) interconnect requirements because of bandwidth-density and power-consumption limitations. However, low-power and high-speed optics-based interconnects are emerging as alternatives for DC and HPC communications; they offer unique opportunities for continued energy-efficiency and bandwidth-density improvements, although cost is a challenge at the shortest length scales. Plasmonics-based interconnects on the other hand, due to their extremely small size, offer another interesting solution for further scaling operational speed and energy efficiency. At the device-level, CMOS compatibility is also an important issue, since ultimately photonics or plasmonics will have to be co-integrated with electronics. In this paper, we survey the available literature and compare the aforementioned interconnect technologies, with respect to their suitability for high-speed and energy-efficient on-chip and off-chip communications. This paper refers to relatively short links with potential applications in the following interconnect distance hierarchy: local group of racks, board to board, module to module, chip to chip, and on chip connections. We compare different interconnect device modules, including low-energy output devices (such as lasers, modulators, and LEDs), photodetectors, passive devices (i.e., waveguides and couplers) and electrical circuitry (such as laserdiode drivers, modulator drivers, transimpedance, and limiting amplifiers). We show that photonic technologies have the potential to meet the requirements for selected HPC and DC applications in a shorter term. We also present that plasmonic interconnect modules could offer ultra-compact active areas, leading to high integration bandwidth densities, and low device capacitances allowing for ultra-high bandwidth operation that would satisfy the application requirements further into the future.

Single Atomic Layer Ferroelectric on Silicon.

A single atomic layer of ZrO2 exhibits ferroelectric switching behavior when grown with an atomically abrupt interface on silicon. Hysteresis in capacitance-voltage measurements of a ZrO2 gate stack demonstrate that a reversible polarization of the ZrO2 interface structure couples to the carriers in the silicon. First-principles computations confirm the existence of multiple stable polarization states and the energy shift in the semiconductor electron states that result from switching between these states. This monolayer ferroelectric represents a new class of materials for achieving devices that transcend conventional complementary metal oxide semiconductor (CMOS) technology. Significantly, a single atomic layer ferroelectric allows for more aggressively scaled devices than bulk ferroelectrics, which currently need to be thicker than 5-10 nm to exhibit significant hysteretic behavior (Park, et al. Adv. Mater. 2015, 27, 1811).

Stable Self-Assembled Atomic-Switch Networks for Neuromorphic Applications

Nature inspired neuromorphic architectures are being explored as an alternative to imminent limitations of conventional complementary metal-oxide semiconductor (CMOS) architectures. Utilization of such architectures for practical applications like advanced pattern recognition tasks will require synaptic connections that are both reconfigurable and stable. Here, we report realization of stable atomic-switch networks (ASN), with inherent complex connectivity, self-assembled from percolating metal nanoparticles (NPs). The device conductance reflects the configuration of synapses which can be modulated via voltage stimulus. By controlling Relative Humidity (RH) and oxygen partial-pressure during NP deposition we obtain stochastic conductance switching that is stable over several months. Detailed characterization reveals signatures of electric-field induced atomic-wire formation within the tunnel-gaps of the oxidized percolating network. Finally we show that the synaptic structure can be reconfigured by stimulating at different repetition rates, which can be utilized as short-term to long-term memory conversion. This demonstration of stable stochastic switching in ASNs provides a promising route to hardware implementation of biological neuronal models and, as an example, we highlight possible applications in Reservoir Computing (RC).

Design and simulation of electrostatic NEMS logic gates

PurposeThis paper aims to present a design and simulation of electrostatic nanoelectromechanical system (NEMS)-based logic gates using laterally actuated cantilever with double-electrode structure that can implement logic functions, similar to logic devices that are made of solid-state transistors which operates at 5 V.Design/methodology/approachThe analytical modeling of NEMS switch is carried out for finding the pull-in and pull-out voltage based on Euler-Bernoulli’s beam theory, and its numerical simulation is performed using finite element method computer-aided design tool COVENTORWARE.FindingsThis paper reports analytical and numerical simulation of basic NEMS switch to realize the logic gates. The proposed logic gate operates on 5 V which suits well with conventional complementary metal oxide semiconductor (CMOS) logic which in turn reduces the power consumption of the device.Originality/valueThe proposed logic gates use a single bit NEMS switch per logic instead of using 6-14 individual transistors as in CMOS. One exclusive feature of this proposed logic gates is that the basic NEMS switch is structurally modified to function as specific logic gates depending upon the given inputs.

An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators

As we enter an era witnessing the closer end of Dennard scaling, where further reduction in power supply-voltage to reduce power consumption becomes more challenging in conventional systems, a goal of developing a system capable of performing large computations with minimal area and power overheads needs more optimization aspects. A rigorous exploration of alternate computing techniques, which can mitigate the limitations of Complementary Metal-Oxide Semiconductor (CMOS) technology scaling and conventional Boolean systems, is imperative. Reflecting on these lines of thought, in this article we explore the potential of non-Boolean computing employing nano-oscillators for performing varied functions. We use a two coupled nano-oscillator as our basic computational model and propose an architecture for a non-Boolean coupled oscillator based co-processor capable of executing certain functions that are commonly used across a variety of approximate application domains. The proposed architecture includes an accuracy tunable knob, which can be tuned by the programmer at runtime. The functionality of the proposed co-processor is verified using a soft coupled oscillator model based on Kuramoto oscillators. The article also demonstrates how real-world applications such as Vector Quantization, Digit Recognition, Structural Health Monitoring, and the like, can be deployed on the proposed model. The proposed co-processor architecture is generic in nature and can be implemented using any of the existing modern day nano-oscillator technologies such as Resonant Body Transistors (RBTs), Spin-Torque Nano-Oscillators (STNOs), and Metal-Insulator Transition (MITs) . In this article, we perform a validation of the proposed architecture using the HyperField Effect Transistor (FET) technology-based coupled oscillators, which provide improvements of up to 3.5× increase in clock speed and up to 10.75× and 14.12× reduction in area and power consumption, respectively, as compared to a conventional Boolean CMOS accelerator executing the same functions.

Reversible binary subtractor design using quantum dot-cellular automata

In the field of nanotechnology, quantum dot-cellular automata (QCA) is the promising archetype that can provide an alternative solution to conventional complementary metal oxide semiconductor (CMOS) circuit. QCA has high device density, high operating speed, and extremely low power consumption. Reversible logic has widespread applications in QCA. Researchers have explored several designs of QCA-based reversible logic circuits, but still not much work has been reported on QCA-based reversible binary subtractors. The low power dissipation and high circuit density of QCA pledge the energy-efficient design of logic circuit at a nano-scale level. However, the necessity of too many logic gates and detrimental garbage outputs may limit the functionality of a QCA-based logic circuit. In this paper we describe the design and implementation of a DG gate in QCA. The universal nature of the DG gate has been established. The QCA building block of the DG gate is used to achieve new reversible binary subtractors. The proposed reversible subtractors have low quantum cost and garbage outputs compared to the existing reversible subtractors. The proposed circuits are designed and simulated using QCA Designer-2.0.3.

Sub-60-mV/decade Negative Capacitance FinFET With Sub-10-nm Hafnium-Based Ferroelectric Capacitor

The negative capacitance (NC) of ferroelectric materials has paved the way for achieving sub-60-mV/decade switching feature in complementary metal-oxide-semiconductor (CMOS) field-effect transistors, by simply inserting a ferroelectric thin layer in the gate stack. However, in order to utilize the ferroelectric capacitor (as a breakthrough technique to overcome the Boltzmann limit of the device using thermionic emission process), the thickness of the ferroelectric layer should be scaled down to sub-10-nm for ease of integration with conventional CMOS logic devices. In this paper, we demonstrate an NC fin-shaped field-effect transistor (FinFET) with a 6-nm-thick HfZrO ferroelectric capacitor. The performance parameters of NC FinFET such as on-/off-state currents and subthreshold slope are compared with those of the conventional FinFET. Furthermore, a repetitive and reliable steep switching feature of the NC FinFET at various drain voltages is demonstrated.

Post-layout simulation of an ultra-low-power OTA using DTMOS input differential pair

ABSTRACTIn this paper, an ultra-low-power dynamic threshold voltage metal-oxide-semiconductor (DTMOS) amplifier is presented. In order to have a high open-loop gain and keep power consumption as low as possible, DTMOS differential pair at input stage technique has been used to improve the specifications of a conventional complementary metal-oxide-semiconductor (CMOS) amplifier such as power supply voltage and power consumption with a proper open-loop gain and unity gain bandwidth. The gain-stage compensation method has been used to overcome the stability problem. The proposed amplifier has been successfully validated and verified in TSMC 0.18 µm CMOS technology and post-layout simulated with Cadence Virtuoso. The post-layout simulation results show that the proposed operational transconductance amplifier (OTA) has 82.77 dB open-loop gain and total power consumption is about 163 nW with 0.4 V voltage supply which is suitable for low-power applications. In the final section in order to evaluate the OTA prefabrication performances, Monte Carlo and corner processes analysis have been performed. Acceptable output swing of 0.37 V is one of the additional features of the proposed OTA.

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers

Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlO), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers.

Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications

To allow fast communication—at several Gb/s—of multimedia content among processors and memories in a multi-processor system-on-chip, a new approach is emerging in literature: Wireless Network-on-Chip (WiNoC). With reference to this scenario, this paper presents the design of the key element of the WiNoC: the antenna. Specifically, a bow-tie antenna is proposed, which operates at mm-waves and can be implemented on-chip using the top metal layer of a conventional silicon CMOS (Complementary Metal Oxide Semiconductor) technology. The antenna performance is discussed in the paper and is compared to the state-of-the-art, including the zig-zag antenna topology that is typically used in literature as a reference for WiNoC. The proposed bow-tie antenna design for WiNoC stands out for its good trade-off among bandwidth, gain, size and beamwidth vs. the state-of-the-art.

A novel high-speed CMOS circuit based on a gang of capacitors

ABSTRACTThere is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from the relatively sluggish operation. In this paper, a circuit that contains a gang of capacitors sharing their charge with each other is proposed as an alternative to long N-channel MOS and P-channel MOS stacks. The proposed scheme is investigated quantitatively and verified by simulation using the 45-nm CMOS technology with VDD = 1 V. The time delay, area and power consumption of the proposed scheme are investigated and compared with the conventional static CMOS logic circuit. It is verified that the proposed scheme achieves 52% saving in the average propagation delay for eight inputs and that it has a smaller area compared to the conventional CMOS logic when the number of inputs exceeds three and a smaller power consumption for a number of inputs exceeding two. The impacts of process variations, component mismatches and technology scaling on the proposed scheme are also investigated.

Designing efficient QCA even parity generator circuits with power dissipation analysis

In the era of modern digital technology, highly scaled and ultra-low power consuming devices have drawn a considerable attention. Quantum-dot Cellular Automata (QCA) are such an emerging nanotechnology that dispenses a highly dense and ultra-low power consuming binary information encoding paradigm. This potential merit instigated the QCA to be an excellent alternative to the conventional Complementary Metal-Oxide-Semiconductor (CMOS) technology. In this paper, we are going to introduce highly scaled and ultra-low power consuming 4, 8, 16 and 32-bit even parity generator circuits. The proposed 4-bit even parity circuit requires 72% fewer cells and occupies 78% less area as compared to previous best designs. Besides, the proposed 32-bit even parity design occupies only 0.283µm2 whereas the previous best reported design occupies 2.08µm2 area. The simulation outcomes reveal that our presented designs have considerable enhancements in terms of cell counts, area and power consumption aspects. In addition, to design and verify the proposed layout, QCADesigner is employed and power dissipation is estimated using QCAPro.