Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs

Abstract

As an emerging nonvolatile device, ferroelectric field-effect transistors (FeFETs) have the potential to reduce the power and area by integrating nonvolatile storage elements with logic. The hysteretic behavior allows an FeFET to function as both a nonvolatile storage element and a switch. This paper exploits this feature of FeFETs to design lookup tables (LUTs) and routing switches, which have obvious utility in field-programmable gate arrays (FPGAs). Read and write schemes are also designed for the proposed LUTs and routing switches. Evaluation results based on a calibrated FeFET model show that the proposed designs are competitive in power and performance. For example, compared with conventional complementary metal–oxide–semiconductor (CMOS)-based equivalents, the proposed FeFET-based LUTs and routing elements improve the power-delay product (PDP) by 5.8– $16\times $ , respectively, while compared with resistive random-access memory (RRAM)-based equivalents, the proposed designs improve the PDP by 1.14– $1.8\times $ . The area of an FeFET-based FPGA is 8% smaller than a conventional CMOS-based FPGA.