Complementary Metal Oxide Semiconductor Process Research Articles

A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits.

To realize a large-scale Spiking Neural Network (SNN) on hardware for mobile applications, area and power optimized electronic circuit design is critical. In this work, an area and power optimized hardware implementation of a large-scale SNN for real time IoT applications is presented. The analog Complementary Metal Oxide Semiconductor (CMOS) implementation incorporates neuron and synaptic circuits optimized for area and power consumption. The asynchronous neuronal circuits implemented benefit from higher energy efficiency and higher sensitivity. The proposed synapse circuit based on Binary Exponential Charge Injector (BECI) saves area and power consumption, and provides design scalability for higher resolutions. The SNN model implemented is optimized for 9 × 9 pixel input image and minimum bit-width weights that can satisfy target accuracy, occupies less area and power consumption. Moreover, the spiking neural network is replicated in full digital implementation for area and power comparisons. The SNN chip integrated from neuron and synapse circuits is capable of pattern recognition. The proposed SNN chip is fabricated using 180 nm CMOS process, which occupies a 3.6 mm2 chip core area, and achieves a classification accuracy of 94.66% for the MNIST dataset. The proposed SNN chip consumes an average power of 1.06 mW—20 times lower than the digital implementation.

Complementary Photo-Synapses Based on Light-Stimulated Porphyrin-Coated Silicon Nanowires Field-Effect Transistors (LPSNFET).

Neuromorphic computing has emerged as the high-energy-efficiency and intelligent solution for processing sensory data. As a potential alternative to neuromorphic computing, photo-excited synaptic systems can integrate the functions of optoelectronic sensing and synaptic computing to realize the low-power and high-performance visual perception. However, one major challenge in high-efficient photo-excited synaptic system is to realize the complementarily enhanced and inhibited synaptic behaviors with small hardware cost as possible. Another challenge is to fabricate the photo-synapse devices with complementary metal oxide semiconductor (CMOS)-compatible process to achieve high enough integration density for practical application. Here, a CMOS-compatible Light-stimulated Porphyrin-coated Silicon Nanowire Field Effect Transistor (LPSNFET) technology is proposed and developed to form the complementary photo-synapses with only two CMOS-like transistors. LPSNFET exhibits fivefold improvement in photo-sensitivity compared to the bare silicon nanowire (SiNW) devices, and can still show obvious responses when incident illumination power is as low as 0.1 mW cm-2 . Moreover,itenables tunable dynamic synaptic plasticity and versatile synaptic functions. Especially, the complementarily enhanced and inhibited behaviors can be realized by modulating SiNW/porphyrin interface via simply changing the MOS type of LPSNFET, which acts like the photonic counterpart of CMOS technology to provide the basic brick for building complex neuromorphic circuits efficiently and economically. Finally, the CMOS process compatibility of LPSNFET provides potential application in future large scale in-sensor computing.

CMOS-MEMS technologies for the applications of environment sensors and environment sensing hubs

The booming growth in environmental conditions sensing and monitoring pushes the need of inexpensive environment sensors with small size and low power consumption. The outbreak of COVID-19 further increases the need for fast monitoring of environment conditions. The micro-electrical-mechanical-systems (MEMS) technologies are considered as promising solutions to realize the required environment sensors. The mature complementary metal-oxide-semiconductor (CMOS) process platforms available in many foundries can be extended to fabricate MEMS sensors to offer the advantage of relatively easier commercialization. Moreover, by leveraging the characteristics of CMOS process platforms, the integration of multiple sensors and sensing circuits to form a compact sensing system can also be achieved. This review paper will focus on introducing the miniaturized environmental sensing devices implemented and integrated using the CMOS-MEMS technologies. In general, the CMOS chips for environment sensing are firstly fabricated using the foundry-available CMOS processes, and then the post-CMOS micromachining processes are performed to implement the CMOS-MEMS environment sensors. This paper respectively reviews five different environment sensors (including the infrared, pressure (barometer), humidity/temperature, and gas sensors) using the CMOS-based MEMS technologies. The advantages and design concerns of sensors fabricated by different CMOS and post-CMOS processes are introduced and discussed. Moreover, the CMOS-MEMS environment sensing hub implemented through the monolithic integration of multiple environment sensors is also introduced.

Power and area‐efficient static current mode logic frequency divider in 180‐nm complementary metal‐oxide‐semiconductor technology

AbstractThis paper presents power and area optimized, high‐speed metal‐oxide‐semiconductor (MOS) current mode logic (MCML)‐based frequency dividers. Each differential pair in the divider is sized separately to minimize the overall power consumption. The divide‐by‐2 frequency divider has been realized in a 180‐nm complementary MOS (CMOS) process technology, and postlayout simulation results show that the proposed frequency divider can work up to an operating frequency of 18.8 GHz in the worst‐case process corner with a maximum power dissipation of 1.715 mW under 1.8‐V supply. It gives a bandwidth of 19.9 GHz which ranges from 1 to 20.9 GHz. The divider occupies a 0.106 × 0.09 mm2 area. The performance corresponds to the figure of merit (FoM) of 43.61 dB. The same optimized latches and two EX‐OR gates are used to design a divide‐by‐5 frequency divider that is also realized in 180‐nm CMOS process technology. The postlayout simulation results show that the proposed divide‐by‐5 frequency divider can faithfully work up to an operating frequency of 12.12 GHz in worst‐case process corner with an excellent power head performance. The maximum power dissipation of the core circuit is 1.39 mW under 1.8‐V supply. It occupies a 0.166 × 0.116 mm2 area. The performance corresponds to the FoM of 26.56 dB which compares favorably with the state of the art.

Guiding Students to Understand the Nanoscale Charge Transport by the Mechanically Controllable Break Junction Technique

Fabrication of molecular devices will meet the demands of the miniaturization of traditional electronic devices. Although microfabrication based on the complementary metal-oxide–semiconductor process can fabricate high-quality single-molecule devices, the cost is high, leading to a challenge to provide a hands-on experiment in the teaching practice of charge transport through single-molecule devices. Here, we demonstrate the low cost and simple procedures associated with a mechanically controllable break junction (MCBJ) technique to fabricate single-molecule devices. On the basis of the MCBJ technique, the conductance of gold–gold atomic contacts and single-molecule junctions can be readily characterized. The teaching practice helps students understand charge transport at the single-molecule level, that is, the quantum tunneling mechanisms. Moreover, the MCBJ technique study provides students the opportunity to develop interdisciplinary thinking, which is vital for understanding, designing, and developing single-molecule electronics.

Efficient Er/O Doped Silicon Photodiodes at Communication Wavelengths by Deep Cooling

AbstractWide band infrared photodetectors have found a wide range of applications in sensing, communication, and spectral analysis. However, the commonly used infrared photodetectors are based on Ge and III‐V semiconductors which are not complementary metal‐oxide‐semiconductor (CMOS) compatible and therefore have limited applications. There is a huge demand for silicon‐based infrared photodetectors due to its low‐cost and compatibility with CMOS processes. Nevertheless, the spectral bandwidth of Si photodetectors is limited to wavelengths below 1.1 µm. Several approaches are developed to extend Si photodetection bandwidth to communication wavelengths. Er/O doped Si is a promising approach which, however, suffers from low infrared responsivities at room temperature when the samples are treated with the standard rapid thermal annealing (RTA). In this work, a novel deep cooling process to treat Er/O doped silicon waveguide photodiodes is applied. In comparison with RTA process, the deep cooling process reduces the defect concentration in silicon by two orders of magnitude, resulting in a two‐orders‐of‐magnitude reduction in leakage current density and an enhanced photoresponsivity to 100 mA W−1 at 1510 nm. The 3dB bandwidth of the silicon waveguide photodiode reaches 30 kHz. The device performance can be further improved by optimizing the deep cooling condition and Er/O doping concentration.

On-Chip Cyclic Voltammetry Measurements Using a Compact 1024-Electrode CMOS IC.

Complementary metal–oxide–semiconductor (CMOS) microelectrode arrays integrate amplifier arrays with on-chip electrodes, offering high-throughput platforms for electrochemical sensing with high spatial and temporal resolution. Such devices have been developed for highly parallel constant voltage amperometric detection of transmitter release from multiple cells with single-vesicle resolution. Cyclic voltammetry (CV) is an electrochemical method that applies voltage waveforms, which provides additional information about electrode properties and about the nature of analytes. A 16-channel, 64-electrode-per-channel CMOS integrated circuit (IC) fabricated in a 0.5 μm CMOS process for CV is demonstrated. Each detector consists of only 11 transistors and an integration capacitor with a unit dimension of 0.0015 mm2. The device was postfabricated using Pt as the working electrode material with a shifted electrode design, which makes it possible to redefine the size and the location of working electrodes. The system incorporating cell-sized (8 μm radius) microelectrodes was validated with dopamine injection tests and CV measurements of potassium ferricyanide at a 1 V/s scanning rate. The cyclic voltammograms were in excellent agreement with theoretical predictions. The technology enables rigorous characterization of electrode performance for the application of CMOS microelectrode arrays in low-noise amperometric measurements of quantal transmitter release as well as other biosensing applications.

MPPT Circuit Using Time Exponential Rate Perturbation and Observation for Enhanced Tracking Efficiency for a Wide Resistance Range of Thermoelectric Generator

The thermoelectric generator (TEG) stands out among many energy harvesters due to its simple structure, small size, rich thermal energy, and the absence of pollution and noise. However, previous studies have rarely probed into the influence of TEG internal resistances on extracting maximum power from TEGs, and the tracking of efficiency is limited. By analyzing the relationship between the tracking efficiency and the TEG internal resistances, a time exponential rate perturbation and observation (P&O) technology is proposed to achieve maximum power point tracking (MPPT) for a wide resistance range of the TEG. Using the time exponential rate P&O, the MPPT circuit observed the power change by comparing the positive-channel metal-oxide semiconductor (PMOS) on-time and perturbs the power by adjusting the negative-channel metal-oxide semiconductor (NMOS) on-time exponentially. The MPPT circuit was implemented in a 110 nm complementary metal-oxide semiconductor (CMOS) process. The tracking efficiency maintained a high level from 98.9 to 99.5%. The applicable range of the TEG resistance was from 1 to 12 Ω, which reflects an enhancement of at least 2.2 times.

Design of Fractional-Order Lead Compensator for a Car Suspension System Based on Curve-Fitting Approximation

An alternative procedure for the implementation of fractional-order compensators is presented in this work. The employment of a curve-fitting-based approximation technique for the approximation of the compensator transfer function offers improved accuracy compared to the Oustaloup and Padé methods. As a design example, a lead compensator intended for usage in car suspension systems is realized. The open-loop and closed-loop behavior of the system is evaluated by post-layout simulation results obtained using the Cadence IC design suite and the Metal Oxide Semiconductor (MOS) transistor models provided by the Austria Mikro Systeme 0.35 m Complementary Metal Oxide Semiconductor (CMOS) process. The derived results verify the efficient performance of the introduced implementation.

Memristive Stochastic Computing for Deep Learning Parameter Optimization

Stochastic Computing (SC) is a computing paradigm that allows for the low-cost and low-power computation of various arithmetic operations using stochastic bit streams and digital logic. In contrast to conventional representation schemes used within the binary domain, the sequence of bit streams in the stochastic domain is inconsequential, and computation is usually non-deterministic. In this brief, we exploit the stochasticity during switching of probabilistic Conductive Bridging RAM (CBRAM) devices to efficiently generate stochastic bit streams in order to perform Deep Learning (DL) parameter optimization, reducing the size of Multiply and Accumulate (MAC) units by 5 orders of magnitude. We demonstrate that in using a 40-nm Complementary Metal Oxide Semiconductor (CMOS) process our scalable architecture occupies 1.55mm$^2$ and consumes approximately 167$\mu$W when optimizing parameters of a Convolutional Neural Network (CNN) while it is being trained for a character recognition task, observing no notable reduction in accuracy post-training.

Emerging Fluorite‐ and Wurtzite‐Type Ferroelectrics: From (Hf,Zr)O2 to AlN and Related Materials

Emerging Fluorite‐ and Wurtzite‐Type Ferroelectrics: From (Hf,Zr)O₂ to AlN and Related Materials

Design and tool flow of a reconfigurable asynchronous neural network accelerator

Convolutional Neural Networks (CNNs) are widely used in computer vision, natural language processing, and so on, which generally require low power and high efficiency in real applications. Thus, energy efficiency has become a critical indicator of CNN accelerators. Considering that asynchronous circuits have the advantages of low power consumption, high speed, and no clock distribution problems, we design and implement an energy-efficient asynchronous CNN accelerator with a 65 nm Complementary Metal Oxide Semiconductor (CMOS) process. Given the absence of a commercial design tool flow for asynchronous circuits, we develop a novel design flow to implement Click-based asynchronous bundled data circuits efficiently to mask layout with conventional Electronic Design Automation (EDA) tools. We also introduce an adaptive delay matching method and perform accurate static timing analysis for the circuits to ensure correct timing. The accelerator for handwriting recognition network (LeNet-5 model) is implemented. Silicon test results show that the asynchronous accelerator has 30% less power in computing array than the synchronous one and that the energy efficiency of the asynchronous accelerator achieves 1.538 TOPS/W, which is 12% higher than that of the synchronous chip.

Post-CMOS Compatible Aluminum Scandium Nitride/2D Channel Ferroelectric Field-Effect-Transistor Memory.

Recent advances in oxide ferroelectric (FE) materials have rejuvenated the field of low-power, nonvolatile memories and made FE memories a commercial reality. Despite these advances, progress on commercial FE-RAM based on lead zirconium titanate has stalled due to process challenges. The recent discovery of ferroelectricity in scandium-doped aluminum nitride (AlScN) presents new opportunities for direct memory integration with logic transistors due to the low temperature of AlScN deposition (approximately 350 °C), making it compatible with back end of the line integration on silicon logic. Here, we present a FE-FET device composed of an FE-AlScN dielectric layer integrated with a two-dimensional MoS2 channel. Our devices show an ON/OFF ratio of ∼106, concurrent with a normalized memory window of 0.3 V/nm. The devices also demonstrate stable memory states up to 104 cycles and state retention up to 105 s. Our results suggest that the FE-AlScN/2D combination is ideal for embedded memory and memory-based computing architectures.

Circuit Level Realization of Low Latency Radix-4 Booth Scheme for Parallel Multipliers

A novel radix-4 Booth encoding scheme has been presented in this paper. By means of the modified truth table, the transistor level delay from inputs to the partial products has been reduced to four transistors. Also, the output waveforms are free of glitch due to the utilization of pass-transistor logic. The calculation of propagation delay for the critical path has been provided to show the superior speed performance of the proposed architecture. Based on the simulation results using HSPICE for Taiwan semiconductor manufacturing company 0.18 µm standard complementary metal–oxide–semiconductor process and 1.8 V power supply, a speed improvement of 24% is obtained compared to the previous architectures when the proposed scheme along with the best reported works have been redesigned and simulated in the same technology platform.

Dispersive readout of reconfigurable ambipolar quantum dots in a silicon-on-insulator nanowire

We report on ambipolar gate-defined quantum dots in silicon on insulator nanowires fabricated using a customized complementary metal–oxide–semiconductor process. The ambipolarity was achieved by extending a gate over an intrinsic silicon channel to both highly doped n-type and p-type terminals. We utilize the ability to supply ambipolar carrier reservoirs to the silicon channel to demonstrate an ability to reconfigurably define, with the same electrodes, double quantum dots with either holes or electrons. We use gate-based reflectometry to sense the inter-dot charge transition (IDT) of both electron and hole double quantum dots, achieving a minimum integration time of 160 (100) μs for electrons (holes). Our results present the opportunity to combine, in a single device, the long coherence times of electron spins with the electrically controllable hole spins in silicon.

Broadband all-silicon hybrid plasmonic TM-pass polarizer using bend waveguides

A complementary–metal–oxide semiconductor (CMOS) compatible all-silicon TM-pass polarizer using plasmonic bends is proposed. To simplify the fabrication and be compatible with the CMOS process, we employ only two materials: silicon and silicon dioxide. Highly doped silicon is used to support the plasmons. We obtain an extinction ratio and an insertion loss of 45.4 and 1.7 dB, respectively, at 1550 nm and a maximum extinction ratio of 58 dB. This is the highest reported extinction ratio for a TM-pass polarizer to the best of our knowledge. Furthermore, we achieved >20 dB of extinction ratio and <2 dB of insertion loss over 72 nm bandwidth for a device footprint <8.8 × 5.4 μm2. To achieve this, we exploit the properties of tight bends in plasmonic waveguides. Another advantage of the device is that it is robust against fabrication variations.

Ten-Bit 0.909-MHz 8-Channel Dual-Mode Successive Approximation ADC for a BLDC Motor Drive

This paper presents a 10-bit 0.909-MHz 8-channel dual-mode successive approximation (SAR) analogue-to-digital converter (ADC) for brushless direct current (BLDC) motor drive, using a Taiwan Semiconductor Manufacturing (TSMC) 0.25 μm 1P3M Complementary Metal Oxide Semiconductor (CMOS) process. The sample-and-hold (S/H) circuit operates with two sampling modes. One is individually sampling eight channels in sequence with an S/H circuit and the other is sampling four channels simultaneously with four S/H circuits. All sampled data will be digitized with high-speed SAR ADC in time division multiplexing (TDM). A dynamic latch-type comparator is utilized to latch the output at an upper or lower level. The advantage of the designed comparator is that it performs with positive feedback to quickly complete the latch function. The double-tail latch-type architecture is utilized to mitigate the significant kickback effect by separating the pre-amplifier stage from the latch. By integrating an input NMOSFET with an input PMOSFET, the designed latch-type comparator can perform with full-swing input voltage. Measurements show that the signal-to-noise ratio (SNR), signal-to-noise-and-distortion ratio (SNDR), effective number of bits (ENOB), power consumption, and chip area are 50.56 dB, 57.03 dB, 8.11 bits, 833 μW, and 1.35 × 0.98 mm2, respectively. The main advantages of the proposed multichannel dual-mode SAR ADC are its low power consumption of 833 μW and high measured resolution of 8.11 bits.

A power amplifier with bandwidth expansion and linearity enhancement in 130 nmcomplementary metal‐oxide‐semiconductorprocess

A power amplifier with bandwidth expansion and linearity enhancement in 130 nm complementary metal-oxide-semiconductor (CMOS) process is presented. A LC connected dual-resonant network is proposed to achieve good broadband performance and high out-band rejection capability simultaneously. Furthermore, the advanced multiple-gated transistor technique is employed to cancel out odd-order intermodulation and harmonic distortions. The PA is implemented in 130 nm CMOS process with an area of 1.17 mm × 0.92 mm. Measurement results demonstrate that the PA exhibits a peak power gain of 8 dB with a relative bandwidth of 38% while maintaining a low reflection coefficient of −23.2 dB, maximum saturation output power of 15.6 dBm, maximum OP1dB and OIP3 of 14.3 dBm and 19 dBm, and a peak power added efficiency of 21.3%, respectively. In addition, an out-band rejection of 20 dB and 23.2 dB at 6.1 GHz and 14 GHz are measured.

Inductance Simulators and Their Application to the 4th Order Elliptic Lowpass Ladder Filter Using CMOS VD-DIBAs

This paper presents inductance simulators using the voltage differencing differential input buffered amplifier (VD-DIBA) as an active building block. Three types of inductance simulators, including floating lossless inductance, series inductance-resistance, and parallel inductance-resistance simulators, are proposed, in addition to their application to the 4th order elliptic lowpass ladder filter. The simple design procedures of these inductance simulators using a circuit block diagram are also given. The proposed inductance simulators employ two VD-DIBAs and two passive elements. The complementary metal oxide semiconductor (CMOS) VD-DIBA used in this design utilizes the multiple-input metal oxide semiconductor (MOS) transistor technique in order to achieve a compact and simple structure with a minimum count of transistors. Thanks to this technique, the VD-DIBA offers high performances compared to the other CMOS structures presented in the literature. The CMOS VD-DIBAs and their applications are designed and simulated in the Cadence environment using a 0.18 µm CMOS process from Taiwan semiconductor manufacturing company (TSMC). Using a supply voltage of ±0.9 V, the linear operation of VD-DIBA is obtained over a differential input range of −0.5 V to 0.5 V. The lowpass (LP) ladder filter realized with the proposed inductance simulators shows a dynamic range (DR) of 80 dB for a total harmonic distortion (THD) of 2% at 1 kHz and a 1.8 V peak-to-peak output. In addition, the experimental results of the floating inductance simulators and their applications are obtained by using VD-DIBA constructed from the available commercial components LM13700 and AD830. The simulation results are in agreement with the experimental ones, confirming the advantages of the inductance simulators and their application.

A Novel Ultrasonic TOF Ranging System Using AlN Based PMUTs.

This paper presents a high-accuracy complementary metal oxide semiconductor (CMOS) driven ultrasonic ranging system based on air coupled aluminum nitride (AlN) based piezoelectric micromachined ultrasonic transducers (PMUTs) using time of flight (TOF). The mode shape and the time-frequency characteristics of PMUTs are simulated and analyzed. Two pieces of PMUTs with a frequency of 97 kHz and 96 kHz are applied. One is used to transmit and the other is used to receive ultrasonic waves. The Time to Digital Converter circuit (TDC), correlating the clock frequency with sound velocity, is utilized for range finding via TOF calculated from the system clock cycle. An application specific integrated circuit (ASIC) chip is designed and fabricated on a 0.18 μm CMOS process to acquire data from the PMUT. Compared to state of the art, the developed ranging system features a wide range and high accuracy, which allows to measure the range of 50 cm with an average error of 0.63 mm. AlN based PMUT is a promising candidate for an integrated portable ranging system.