Complementary Metal Oxide Semiconductor Process Research Articles

저전력 24-GHz CMOS 믹서 설계

This paper proposes a low-power 24-GHz CMOS down-conversion mixer for the automotive radar. This circuit operates at the operation frequency of 24 GHz, and it contains low-power circuit technique. The proposed circuit is also fabricated using 65-nm RF CMOS(radio frequeny complementary metal-oxide-semiconductor) process. The circuit is powered using a 1.2-V supply with the bias voltage of 0.8 V for the low-power technique. This circuit also has fully-differential scheme to reduce RF noise, and harmonic distortions. The proposed mixer showed lower power dissipation of 6.5 mW with a high conversion gain and very small chip area of 0.01 mm2 as compared to conventional research results.

Ultra-Low Power Hand Gesture Sensor Using Electrostatic Induction

This paper presents an ultra-low power hand gesture sensor using electrostatic induction for mobile devices. Two electrodes, which consist of electret foils stacked on metal sheets, are used to recognize two gestures such as hand movements from left to right and right to left. The hand gesture recognition is realized by detecting the electrostatic induction currents induced by hand movements. However, the electrostatic induction currents are significantly small; hence, a hand gesture recognition chip is first designed in this study to amplify and detect the small electrostatic induction currents with low power. This chip is fabricated in a commercial 180 nm complementary metal oxide semiconductor (CMOS) process, and the measurement results indicate that the fabricated gesture recognition chip consumes 406 nW, which is less than 1/100th of the power dissipation of conventional gesture sensors.

High mobility SiMOSFETs fabricated in a full 300 mm CMOS process

The quality of the semiconductor–barrier interface plays a pivotal role in the demonstration of high quality reproducible quantum dots for quantum information processing. In this work, we have measured SiMOSFET Hall bars on undoped Si substrates in order to investigate the device quality. For devices fabricated in a full complementary metal oxide semiconductor (CMOS) process and of very thin oxide below a thickness of 10 nm, we report a record mobility of 17.5 × 103 cm2 V−1 s−1 indicating a high quality interface, suitable for future qubit applications. We also study the influence of gate materials on the mobilities and discuss the underlying mechanisms, giving insight into further material optimization for large scale quantum processors.

Electromechanically Tunable Frequency‐agile Metamaterial Bandpass Filters for Terahertz Waves

AbstractTunable terahertz (THz) transmission filters are essential for various key applications including miniaturized spectrometers, hyperspectral imagers, and channel selectors in high‐speed wireless communication systems. However, tunable THz transmission filters have remained elusive, so far. Here, an electromechanically reconfigurable microcantilevers integrated complementary metamaterial to function as a frequency‐agile THz bandpass transmission filter is reported. A large tunable range of 70% at central frequency of 0.455 THz is designed, and the experimental results show active switching of THz transmission frequency range of 54% at central frequency of 0.5 THz. The proposed electromechanically reconfigurable metadevice provides a large tunable range, uses electrical control, and is fabricated using complementary metal oxide semiconductor (CMOS) compatible materials and processes, thus making it highly attractive for the realization of plethora of miniaturized high‐performance THz components and devices.

ALL-DIGITAL PHASE LOCKED LOOP (ADPLL) TOPOLOGIES FOR RFID SYSTEM APPLICATION: A REVIEW

An all-digital phase locked loop (ADPLL)-based local oscillator (LO) of RF transceiver application such as radio-frequency identification (RFID) system has gained popularity by accessing the benefits in complementary metal-oxide semiconductor (CMOS) process technology. This paper reviews some state-of-art of the ADPLL structures based on their applications and analyses its major implementation block, which is the digital-controlled oscillator (DCO). The DCO is evaluated based on its CMOS scaling and its performance in ADPLL, such as the power consumption, the chip area, the frequency range, the supply voltage, and the phase noise. Based on the review, the reduction in CMOS scaling decreases the transistor size in ADPLL design which leads to a smaller area and a low power dissipation. The combination of the time-to-digital (TDC) and the digital-to-time converter (DTC) that is used as the phase-frequency detector (PFD) in ADPLL is proposed to reduce the power and phase noise performance due to their high linearity design. The delay cell oscillator is found to consume more power at higher operating frequency, but it has an advantage of having less complexity and consuming less power and area in the circuit compared to the LC tank oscillator. For future work, it is recommended that an ADPLL-based LO of RFID transceiver with lowest voltage supply implementation is chosen and the use of the TDC-less as the PFD is selected due to its small area. While for the DCO, the delay cell will be designed due to its simpler implementation and occupy small area.

Un nuevo rectificador reconfigurable CMOS para recolectores de energía piezoeléctrica en dispositivos portables

Wearable energy harvesters have potential application in the conversion of human-motion energy into electrical energy to power smart health-monitoring devices, the textile industry, smartwatches, and glasses. These energy harvesters require optimal rectifier circuits that maximize their charging efficiencies. In this study, we present the design of a novel complementary metal-oxide semiconductor (CMOS) reconfigurable rectifier for wearable piezoelectric energy harvesters that can increase their charging efficiencies. The designed rectifier is based on standard 0.18 µm CMOS process technology considering a geometrical pattern with a total silicon area of 54.765 µm x 86.355 µm. The proposed rectifier circuit has two transmission gates (TG) that are composed of four rectifier transistors with a charge of 45 kΩ, a minimum input voltage of 500 mV and a maximum voltage of 3.3 V. Results of numerical simulations of the rectifier performance indicate a voltage conversion efficiency of 99.4% and a power conversion efficiency up to 63.3%. The proposed rectifier can be used to increase the charging efficiency of wearable piezoelectric energy harvesters.

A Fully Integrated 64-Channel Recording System for Extracellular Raw Neural Signals

This paper presents a fully integrated 64-channel neural recording system for local field potential and action potential. It mainly includes 64 low-noise amplifiers, 64 programmable amplifiers and filters, 9 switched-capacitor (SC) amplifiers, and a 10-bit successive approximation register analogue-to-digital converter (SAR ADC). Two innovations have been proposed. First, a two-stage amplifier with high-gain, rail-to-rail input and output, and dynamic current enhancement improves the speed of SC amplifiers. The second is a clock logic that can be used to align the switching clock of 64 channels with the sampling clock of ADC. Implemented in an SMIC 0.18 μm Complementary Metal Oxide Semiconductor (CMOS) process, the 64-channel system chip has a die area of 4 × 4 mm2 and is packaged in a QFN−88 of 10 × 10 mm2. Supplied by 1.8 V, the total power is about 8.28 mW. For each channel, rail-to-rail electrode DC offset can be rejected, the referred-to-input noise within 1 Hz–10 kHz is about 5.5 μVrms, the common-mode rejection ratio at 50 Hz is about 69 dB, and the output total harmonic distortion is 0.53%. Measurement results also show that multiple neural signals are able to be simultaneously recorded.

A 6–18 GHz high dB‐linear attenuator based on variable gain amplifier for ultra‐wideband phased array systems

AbstractThe letter presents a high dB‐linear attenuator based on variable gain amplifier (VGA) for ultra‐wideband phased array systems. An effective dB‐linear compensation structure is proposed to improve the gain range and accuracy. The bandwidth and gain flatness of the proposed VGA are increased by the emitter resistor–capacitor negative feedback and transistor segmentation technique. The proposed VGA is implemented with the 0.18 μm SiGe bipolar complementary metal oxide semiconductor (BiCMOS) process. The measured results show that the VGA can operate from 6 to 18 GHz with a controlled variable gain range of 20 dB, the root‐mean‐square gain error is less than 0.55 dB. The input 1 dB compression point (IP1dB) of the fabricated VGA is more than −5 dBm. The proposed VGA consumes 71 mW and occupies a chip area of 0.98 mm × 0.98 mm.

A Curvature Compensation Technique for Low-Voltage Bandgap Reference

Based on the standard 40 nm Complementary Metal Oxide Semiconductor (CMOS) process, a curvature compensation technique is proposed. Two low-voltage, low-power, high-precision bandgap voltage reference circuits are designed at a 1.2 V power supply. By adding IPTAT (positive temperature coefficient current) and ICTAT (negative temperature coefficient current) to the output resistance, the first-order compensation bandgap voltages can be obtained. Meanwhile, the third high-order compensation current is also superimposed on the same resistance. We make use of the collector current of the bipolar transistor to compensate for the nonlinear term of VBE. The simulation results show that TC (temperature coefficient) of the first circuit reference could be reduced from 29.1 × 10−6/°C to 5.71 × 10−6/°C over the temperature range of −25 to 125 °C after temperature compensation. The second one could be reduced from 17 × 10−6/°C to 5.22 × 10−6/°C.

A comprehensive review of FET‐based pH sensors: materials, fabrication technologies, and modeling

AbstractThe demand for miniaturized point‐of‐care chemical/biochemical sensors has driven the development of field‐effect transistors (FETs) based pH sensors over the last 50 years. This paper aims to review the fabrication technologies, device structures, sensing film materials, and modeling techniques utilized for FET‐based pH sensors. We present the governing principles of potentiometric sensors, with major focus on the working principles of ion‐sensitive FETs (ISFETs). We extensively review different sensing film materials deposited by various techniques, which is critical to the sensing performance of ISFETs. The popular fabrication technologies have been presented, with special emphasis on state‐of‐the‐art silicon‐on‐insulator based technology, which can achieve high sensitivity by utilizing the dual‐gate effect. Furthermore, recent advancements in nano‐ISFETs has been elucidated. We also discuss the adoption of unmodified complementary metal‐oxide semiconductor (CMOS) ISFETs using standard CMOS processes, which has enabled the fabrication of integrated ISFET arrays, which are especially suited for ion‐imaging applications. Moreover, recent developments in extended‐gate FETs has been discussed, which have gained lot of attention due to their design flexibility and ease of fabrication, which is desirable for wearable sensing applications. In addition, recently there have been efforts to utilize nonsilicon channel materials for pH‐sensing application to obtain superior performance and various channel materials have been reviewed. Finally, we have extensively reviewed the ISFET device modeling and simulation techniques using various computer‐aided design tools, which aid in sensor design and characterization.

Producing Microscale Ge Textures via Titanium Nitride‐ and Nickel‐Assisted Chemical Etching with CMOS‐Compatibility

AbstractAs an emerging anisotropic wet etching technique, metal‐assisted chemical etching (MacEtch) has been widely employed for fabricating nano‐ and micro‐structures of germanium (Ge) for potential infrared (IR) photonics and optoelectronics. However, traditional noble metal catalysts such as Au and Ag limit its application in complementary metal oxide semiconductor (CMOS) processes, as Au is considered as a detrimental deep‐level impurity in Ge. In this work, the feasibility of exploring TiN and Ni as CMOS‐compatible catalysts for Ge MacEtch is investigated. Both TiN and Ni catalysts exhibit inverse MacEtch behavior, resulting in formation of inverted pyramid and v‐groove Ge microscale textures which exhibit outstanding IR antireflection performance. No catalyst delamination of TiN is observed during etching, while it can be avoided by inserting a Ti adhesive layer beneath Ni catalyst. Schottky contact barrier of metal catalyst with Ge is also investigated indicating similar hole injection efficiency among TiN, Ni, and Ti/Ni with Ge junction due to strong Fermi level pinning effect. The TiN‐ and Ni‐assisted chemical etching of Ge shed light on CMOS‐compatible Ge‐based photonic and optoelectronic applications.

A 1.8‐V 240‐MHz 2.19‐mW Four‐Stage CMOS OTA with a Segmenting Frequency Compensation Technique

A four-stage Operational transconductance amplifier (OTA) used in an infrared temperature sensor adopting the proposed Feed-forward Gm-stage and segmenting nested Miller compensation technique is presented. The purpose of the proposed segment compensation is primarily to make more amplifier stages concatenated. The circuit linked several transconductance stages to form a segment, and linked several segments to form a large multistage amplifier. For example, a two-stage amplifier linked with a three-stage amplifier can realize a five-stage amplifier, two three-stage amplifiers linked can realize a six-stage amplifier. A four-stage amplifier in the form of 2+2 (two stages and two stages) was used as an example to verify this compensation method. The proposed OTA is designed in the 180nm complementary metal oxide semiconductor process. It consists of two parts which ensure the stability and improve the bandwidth performance. The first part is a feed-forward transconductance stage, and the second part is the two-segment transconductance stages with the Miller compensation techniques employed within and between the two segments. Based on the small-signal model, stability analysis and theoretical derivation are performed in theory. On condition of a 2-pF load capacitance, a direct current gain of 109dB and a gain-bandwidth of 240MHz with a phase margin of 50° can be achieved. The proposed design consumes 2.19mW in a 1.8-V supply voltage. The transient simulation indicates that the settling time of the output is 19ns with the settling error being 1%, and the slew rate is 114V/μs.

Modeling, Simulation Methods and Characterization of Photon Detection Probability in CMOS-SPAD

Single-Photon Avalanche Diodes (SPAD) in Complementary Metal-Oxide Semiconductor (CMOS) technology are potential candidates for future “Light Detection and Ranging” (Lidar) space systems. Among the SPAD performance parameters, the Photon Detection Probability (PDP) is one of the principal parameters. Indeed, this parameter is used to evaluate the SPAD sensitivity, which directly affects the laser power or the telescope diameter of space-borne Lidars. In this work, we developed a model and a simulation method to predict accurately the PDP of CMOS SPAD, based on a combination of measurements to acquire the CMOS process doping profile, Technology Computer-Aided Design (TCAD) simulations, and a Matlab routine. We compare our simulation results with a SPAD designed and processed in CMOS 180 nm technology. Our results show good agreement between PDP predictions and measurements, with a mean error around 18.5%, for wavelength between 450 and 950 nm and for a typical range of excess voltages between 15 and 30% of the breakdown voltage. Due to our SPAD architecture, the high field region is not entirely insulated from the substrate, a comparison between simulations performed with and without the substrate contribution indicates that PDP can be simulated without this latter with a moderate loss of precision, around 4.5 percentage points.

High PSRR Wide Supply Range Dual-Voltage Reference Circuit for Bio-Implantable Applications

On-chip systems are challenging owing to the limited size of the components, such as the capacitor bank in the rectifier. With a small on-chip capacitor, the output voltage of the rectifier might ring if the circuit experiences significant changes in current. The reference circuit is the first block after the rectifier, and the entire system relies on its robustness. A fully integrated dual-voltage reference circuit for bio-implantable applications is presented. The proposed circuit utilizes nonlinear current compensation techniques that significantly decrease supply variations and reject high-supply ripples for various frequencies. The reference circuit was verified using a 0.35 µm complementary metal-oxide semiconductor (CMOS) process. Maximum PSRR values of −112 dB and −128 dB were obtained. With a supply range from 2.8 to 12 V, the proposed design achieves 0.916 and 1.5 mV/V line regulation for the positive and negative reference circuits, respectively.

Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing

Although multirow read is essential to achieve static random access memory (SRAM) in-memory computing (IMC), it may undermine circuit linearity and computational consistency across columns. In this study, we investigated the causes of nonlinearity and inconsistency. Based on detailed analyses, we proposed a cascade current mirror (CCM) peripheral circuit. Only four transistors were added to each bitline (BL) for voltage clamping and proportionally mirroring the read current. In addition, a 6T SRAM cell with double word lines operating with the CCM further reduced the delay and improved the computational consistency. We applied the structure to numerous prior studies and evaluated them using the 28-nm complementary metal-oxide semiconductor process. The measurement results show that the proposed CCM can reduce the integer nonlinearity by up to 70% at 0.8-V supply, and the computational consistency is substantially improved by 56.84% at 0.9-V supply. In addition, we verified the performance improvement through classification using a convolutional neural network, achieving 91% accuracy in the MNIST and 86% accuracy in the CIFAR-10. The area overhead was 1.77% in a 512×512 SRAM array when integrating the proposed CCM circuit.

A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique

PurposeIn parallel sampling method, the size of the sampling capacitor is reduced to improve the bandwidth of the ADC.Design/methodology/approachVarious low-power techniques for 10-bit 200MS/s pipelined analog-to-digital converter (ADC) are presented. This work comprises two techniques including parallel sampling and switched op-amp sharing technique.FindingsThis paper aims to study the effect of parallel sampling and switched op-amp sharing techniques on power consumption in pipelined ADC. In switched op-amp sharing technique, the numbers of op-amps used in the stages are reduced. Because of the reduction in the size of capacitors in parallel sampling technique and op-amps in the switched op-amp sharing technique, the power consumption of the proposed pipelined ADC is reduced to a greater extent.Originality/valueSimulated the 10-bit 200MS/s pipelined ADC with complementary metal oxide semiconductor process and the simulation results shows a maximum differential non-linearity of +0.31/−0.31 LSB and the maximum integral non-linearity (of +0.74/−0.74 LSB with 62.9 dB SFDR, 55.90 dB SNDR and ENOB of 8.99 bits, respectively, for 18mW power consumption with the supply voltage of 1.8 V.

Folded 15-channel arrayed waveguide gratings on silicon nitride platform with loop reflector

Silicon nitride (Si3N4) arrayed waveguide gratings (AWGs) have been widely used for dense wavelength division multiplexing systems because of their low loss and crosstalk. However, they have larger footprints because of their lower relative index compared with silicon-on-insulator (SOI) devices. In this study, a folded 1×15 Si3N4 AWG was fabricated on an SOI wafer with a silicon photonics loop reflector. The combination of the Si3N4 AWG and the Si loop reflector greatly reduced the device footprint and increased the fabrication tolerances. A layer coupler was used to connect the arrayed waveguides of the AWG to the Si loop reflector. The folded AWG consisted of a half Si3N4 AWG structure, an layer coupler array, and a Si loop reflector array. The measured insertion loss and crosstalk of the designed AWG were -5.46 dB and -17.2 dB, respectively. The integration of the half Si3N4 AWG and the arrayed Si loop reflectors can effectively reduce the large footprint of a Si3N4 AWG device with a standard complementary metal–oxide–semiconductor process while maintaining a relatively high performance.

Extended endurance performance and reduced threshold voltage by doping Si in GeSe-based ovonic threshold switching selectors

Selectors are essential part of the high-density storage architectures to operate the storage device in the crossbar arrays by providing a desired net voltage drop and suppressing undesired current flow. Germanium selenide -based Ovonic Threshold Switching (OTS) selector shows a promising candidate for simple binary composition and high selectivity, however, the high threshold voltage and thermal budget lower than required for Complementary Metal Oxide Semiconductor process are needed to overcome. In this paper, we demonstrate the effect of silicon doping Ge42Se58 thin films on their electrical characteristics of OTS devices and the electronic structure of materials. Si doping allows low threshold voltages ranging from 1.5 to 3 V and improved thermal stability, Si-Ge-Se with Si 13% can cycle steadily more than 5 × 106 cycles. In addition, the optical energy gap of films decreases with increasing Si content. These results, being interpreted as Si atoms modify the bonding type of Ge42Se58 thin film as well as electronic structure includes the energy gap and trap states, suggest an effective method to modulate threshold voltage of the GeSe-based selector by using Si as dopant for various OTS device applications. According to the unified analytical model (Poole-Poole-Frenkel) based on trap-limited conduction, the trap density of Si-Ge-Se thin films in the switching process decreases from 1.29×1017cm−3 to 2.88×1016cm−3with increasing Si content.

An ultralow-power CMOS bandgap voltage reference with N+ doped PMOS

An ultra-low-power and low-area complementary metal oxide semiconductor (CMOS) bandgap voltage reference, without resistor and substrate bipolar, is presented and verified in the TSMC 0.18 μm CMOS process in this paper. By adopting PMOS transistor with N+ doped gate and a new temperature compensation technique, the proposed bandgap demonstrates a power consumption of around 50 nA for a supply voltage of 1.5 V and a temperature coefficient of 75 ppm without trimming. The chip can operate with a supply voltage from 1.2 V to 1.8 V and small area of the bandgap is around 0.001 mm2. The characteristic of the proposed voltage bandgap reference makes it suitable for ultralow-power low-area applications.

A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits.

To realize a large-scale Spiking Neural Network (SNN) on hardware for mobile applications, area and power optimized electronic circuit design is critical. In this work, an area and power optimized hardware implementation of a large-scale SNN for real time IoT applications is presented. The analog Complementary Metal Oxide Semiconductor (CMOS) implementation incorporates neuron and synaptic circuits optimized for area and power consumption. The asynchronous neuronal circuits implemented benefit from higher energy efficiency and higher sensitivity. The proposed synapse circuit based on Binary Exponential Charge Injector (BECI) saves area and power consumption, and provides design scalability for higher resolutions. The SNN model implemented is optimized for 9 × 9 pixel input image and minimum bit-width weights that can satisfy target accuracy, occupies less area and power consumption. Moreover, the spiking neural network is replicated in full digital implementation for area and power comparisons. The SNN chip integrated from neuron and synapse circuits is capable of pattern recognition. The proposed SNN chip is fabricated using 180 nm CMOS process, which occupies a 3.6 mm2 chip core area, and achieves a classification accuracy of 94.66% for the MNIST dataset. The proposed SNN chip consumes an average power of 1.06 mW—20 times lower than the digital implementation.