Complementary Metal Oxide Semiconductor Process Research Articles

Phase Change Metasurfaces by Continuous or Quasi-Continuous Atoms for Active Optoelectronic Integration.

In recent decades, metasurfaces have emerged as an exotic and appealing group of nanophotonic devices for versatile wave regulation with deep subwavelength thickness facilitating compact integration. However, the ability to dynamically control the wave–matter interaction with external stimulus is highly desirable especially in such scenarios as integrated photonics and optoelectronics, since their performance in amplitude and phase control settle down once manufactured. Currently, available routes to construct active photonic devices include micro-electromechanical system (MEMS), semiconductors, liquid crystal, and phase change materials (PCMs)-integrated hybrid devices, etc. For the sake of compact integration and good compatibility with the mainstream complementary metal oxide semiconductor (CMOS) process for nanofabrication and device integration, the PCMs-based scheme stands out as a viable and promising candidate. Therefore, this review focuses on recent progresses on phase change metasurfaces with dynamic wave control (amplitude and phase or wavefront), and especially outlines those with continuous or quasi-continuous atoms in favor of optoelectronic integration.

Low-Noise Chopper Amplifier Using Lateral PNP Input Stage With Automatic Base Current Cancellation

This brief presents a low-noise chopper amplifier that uses a lateral PNP input stage with automatic base current cancellation in complementary metal–oxide–semiconductor (CMOS) process. A bipolar junction transistor (BJT) input stage can achieve lower noise level than the MOS transistor input stage, but its base current causes low DC input impedance. To enhance the DC input impedance of the BJT input stage, an automatic base current cancellation circuit is implemented using a 10-bit current digital-to-analog converter (DAC) and a successive approximation register (SAR) logic. The output current of the DAC tracks the base current of the BJT input stage using a binary search operation of the SAR logic, and the current DAC provides a cancellation current to the base of the BJT input stage to cancel the input base current. The amplifier is implemented in 0.18- $\mu \text{m}$ CMOS process, and the proposed amplifier occupies an active area of 0.297 mm2. The current consumption of the chopper amplifier is 146 $\mu \text{A}$ with 3.3 V supply voltage. The input referred noise of the chopper amplifier is 5.53 nV $/\surd $ Hz. The input bias current of the proposed amplifier with lateral PNP input stage implementing automatic base current cancellation is 0.391 nA.

An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors.

The front-end electronics (FEE) of the Compact Muon Solenoid (CMS) is needed very low power consumption and higher readout bandwidth to match the low power requirement of its Short Strip application-specific integrated circuits (ASIC) (SSA) and to handle a large number of pileup events in the High-Luminosity Large Hadron Collider (LHC). A low-noise, wide bandwidth, and ultra-low power FEE for the pixel-strip sensor of the CMS has been designed and simulated in a 0.35 µm Complementary Metal Oxide Semiconductor (CMOS) process. The design comprises a Charge Sensitive Amplifier (CSA) and a fast Capacitor-Resistor-Resistor-Capacitor (CR-RC) pulse shaper (PS). A compact structure of the CSA circuit has been analyzed and designed for high throughput purposes. Analytical calculations were performed to achieve at least 998 MHz gain bandwidth, and then overcome pileup issue in the High-Luminosity LHC. The spice simulations prove that the circuit can achieve 88 dB dc-gain while exhibiting up to 1 GHz gain-bandwidth product (GBP). The stability of the design was guaranteed with an 82-degree phase margin while 214 ns optimal shaping time was extracted for low-power purposes. The robustness of the design against radiations was performed and the amplitude resolution of the proposed front-end was controlled at 1.87% FWHM (full width half maximum). The circuit has been designed to handle up to 280 fC input charge pulses with 2 pF maximum sensor capacitance. In good agreement with the analytical calculations, simulations outcomes were validated by post-layout simulations results, which provided a baseline gain of 546.56 mV/MeV and 920.66 mV/MeV, respectively, for the CSA and the shaping module while the ENC (Equivalent Noise Charge) of the device was controlled at 37.6 e− at 0 pF with a noise slope of 16.32 e−/pF. Moreover, the proposed circuit dissipates very low power which is only 8.72 µW from a 3.3 V supply and the compact layout occupied just 0.0205 mm2 die area.

Sensitivity, Noise and Resolution in a BEOL-Modified Foundry-Made ISFET with Miniaturized Reference Electrode for Wearable Point-of-Care Applications.

Ion-sensitive field-effect transistors (ISFETs) form a high sensitivity and scalable class of sensors, compatible with advanced complementary metal-oxide semiconductor (CMOS) processes. Despite many previous demonstrations about their merits as low-power integrated sensors, very little is known about their noise characterization when being operated in a liquid gate configuration. The noise characteristics in various regimes of their operation are important to select the most suitable conditions for signal-to-noise ratio (SNR) and power consumption. This work reports systematic DC, transient, and noise characterizations and models of a back-end of line (BEOL)-modified foundry-made ISFET used as pH sensor. The aim is to determine the sensor sensitivity and resolution to pH changes and to calibrate numerical and lumped element models, capable of supporting the interpretation of the experimental findings. The experimental sensitivity is approximately 40 mV/pH with a normalized resolution of 5 mpH per µm2, in agreement with the literature state of the art. Differences in the drain current noise spectra between the ISFET and MOSFET configurations of the same device at low currents (weak inversion) suggest that the chemical noise produced by the random binding/unbinding of the H+ ions on the sensor surface is likely the dominant noise contribution in this regime. In contrast, at high currents (strong inversion), the two configurations provide similar drain noise levels suggesting that the noise originates in the underlying FET rather than in the sensing region.

A 2.53 NEF 8-bit 10 kS/s 0.5 μm CMOS Neural Recording Read-Out Circuit with High Linearity for Neuromodulation Implants

This paper presents a power-efficient complementary metal-oxide-semiconductor (CMOS) neural signal-recording read-out circuit for multichannel neuromodulation implants. The system includes a neural amplifier and a successive approximation register analog-to-digital converter (SAR-ADC) for recording and digitizing neural signal data to transmit to a remote receiver. The synthetic neural signal is generated using a LabVIEW myDAQ device and processed through a LabVIEW GUI. The read-out circuit is designed and fabricated in the standard 0.5 μμm CMOS process. The proposed amplifier uses a fully differential two-stage topology with a reconfigurable capacitive-resistive feedback network. The amplifier achieves 49.26 dB and 60.53 dB gain within the frequency bandwidth of 0.57–301 Hz and 0.27–12.9 kHz to record the local field potentials (LFPs) and the action potentials (APs), respectively. The amplifier maintains a noise–power tradeoff by reducing the noise efficiency factor (NEF) to 2.53. The capacitors are manually laid out using the common-centroid placement technique, which increases the linearity of the ADC. The SAR-ADC achieves a signal-to-noise ratio (SNR) of 45.8 dB, with a resolution of 8 bits. The ADC exhibits an effective number of bits of 7.32 at a low sampling rate of 10 ksamples/s. The total power consumption of the chip is 26.02 μμW, which makes it highly suitable for a multi-channel neural signal recording system.

Universal Filter Based on Compact CMOS Structure of VDDDA.

This paper proposes the simulated and experimental results of a universal filter using the voltage differencing differential difference amplifier (VDDDA). Unlike the previous complementary metal oxide semiconductor (CMOS) structures of VDDDA that is present in the literature, the present one is compact and simple, owing to the employment of the multiple-input metal oxide semiconductor (MOS) transistor technique. The presented filter employs two VDDDAs, one resistor and two grounded capacitors, and it offers low-pass: LP, band-pass: BP, band-reject: BR, high-pass: HP and all-pass: AP responses with a unity passband voltage gain. The proposed universal voltage mode filter has high input impedances and low output impedance. The natural frequency and bandwidth are orthogonally controlled by using separated transconductance without affecting the passband voltage gain. For a BP filter, the root mean square (RMS) of the equivalent output noise is 46 µV, and the third intermodulation distortion (IMD3) is −49.5 dB for an input signal with a peak-to peak of 600 mV, which results in a dynamic range (DR) of 73.2 dB. The filter was designed and simulated in the Cadence environment using a 0.18-µm CMOS process from Taiwan semiconductor manufacturing company (TSMC). In addition, the experimental results were obtained by using the available commercial components LM13700 and AD830. The simulation results are in agreement with the experimental one that confirmed the advantages of the filter.

Microwave functionality of spintronic devices implemented in a hybrid complementary metal oxide semiconductor and magnetic tunnel junction technology

This letter presents magnetic tunnel junction based spintronic devices completely implemented in a hybrid semiconductor process that comprises a complementary metal oxide semiconductor and a magnetic tunnel junction technology. To demonstrate the coexistence of both complementary metal oxide semiconductor circuits and magnetic tunnel junction based spintronic devices, a proof-of-concept circuit prototype comprising 40 spintronic devices and a digital complementary metal oxide semiconductor serial peripheral interface is fabricated. According to measurement results, a selected spintronic device from the magnetic tunnel junction array, when surrounded by an external out-ofplane magnetic field of 1 kOe, emitted microwave signals from 2.235 to 2.464 GHz with an output power from 0.88 to 0.72 nW, when the DC current was increased from 0.6 to 1.0 mA. To the authors' best knowledge, this is the first work demonstrating the functionality of spintronic oscillators fully integrated in complementary metal oxide semiconductor circuit implemented in a hybrid complementary metal oxide semiconductor and magnetic tunnel junction process.

Millimeter-wave dual-mode and dual-band switchable Gilbert up-conversion mixer in 65-nm CMOS process

AbstractIn this paper, a millimeter-wave (MMW) dual-mode and dual-band switchable Gilbert up-conversion mixer in a commercial 65-nm complementary metal oxide semiconductor (CMOS) process is presented. By simply changing the bias, the proposed CMOS Gilbert up-conversion mixer can be switched between subharmonic and fundamental operation modes for MMW dual-band applications. With a low local oscillator pumping power of 3 dBm and low dc power consumption of 6 mW, the proposed CMOS Gilbert up-conversion mixer exhibits a measured conversion gain of −0.5 ± 1.5 dB from 37 to 50 GHz and 2.5 ± 1.5 dB from 17.5 to 32 GHz for the subharmonic and fundamental modes, respectively.

Manufacturing and Testing of Radio Frequency MEMS Switches Using the Complementary Metal Oxide Semiconductor Process.

A radio frequency microelectromechanical system switch (MSS) manufactured by the complementary metal oxide semiconductor (CMOS) process is presented. The MSS is a capacitive shunt type. Structure for the MSS consists of coplanar waveguide (CPW) lines, a membrane, and springs. The membrane locates over the CPW lines. The surface of signal line for the CPW has a silicon dioxide dielectric layer. The fabrication of the MSS contains a CMOS process and a post-process. The MSS has a sacrificial oxide layer after the CMOS process. In the post-processing, a wet etching of buffer oxide etch (BOE) etchant is employed to etch the sacrificial oxide layer, so that the membrane is released. Actuation voltage for the MSS is simulated using the CoventorWare software. The springs have a low stiffness, so that the actuation voltage reduces. The measured results reveal that actuation voltage for the MSS is 10 V. Insertion loss for the MSS is 0.9 dB at 41 GHz and isolation for the MSS is 30 dB at 41 GHz.

High-Speed DD Transmission Using a Silicon Receiver Co-Integrated With a 28-nm CMOS Gain-Tunable Fully-Differential TIA

We report >100-Gb/s direct-detection (DD) transmission using an integrated silicon optical receiver, which comprised a fully-differential 28-nm complementary metal-oxide-semiconductor (CMOS) transimpedance amplifier (TIA) wire-bonded to a Silicon-Germanium (SiGe) balanced photodiode (PD). The fully-differential TIA architecture enabled significant bit-error-rate (BER) and signal-to-noise ratio improvements over a single-output TIA design when introducing it to the DD transmission. We experimentally validated its effectiveness in both back-to-back (B2B) and 2-km long standard single-mode fibre (SSMF) links using 50/100-Gb/s signals, including Nyquist on-off keying (OOK), Nyquist 4-ary pulse amplitude modulation (PAM4), uniformly-loaded DD optical orthogonal frequency division multiplexing (DDO-OFDM) and adaptively-loaded DDO-OFDM. Furthermore, we demonstrate that the integrated optical receiver was capable of balancing the trade-off between its electrical bandwidth and transimpedance gain by simply adjusting a voltage supply to the TIA. Without the need for optical amplification and while keeping the BERs below the 7% forward error correction limit, up to 173.22-Gb/s and 139.86-Gb/s adaptively-loaded DDO-OFDM transmission was achieved for B2B and 2-km transmission, respectively. The demonstrated results highlight the potential of the integrated silicon optical receiver, fabricated using the standard CMOS process for high-speed and short-reach optical interconnects.

Low‐offset differential output switched‐capacitor interface for micro‐capacitive acceleration sensors

This paper presents two simple but effective switched capacitor based differential output capacitive sensor interfaces, designed and fabricated in United Microelectronics Corporation 180 nm complementary metal oxide semiconductor (CMOS) process technology. The first configuration combines chopper modulation and switched capacitor based correlated double sampling, while the second configuration utilises chopper modulation with a modified demodulation scheme to reduce noise and offset. The proposed designs utilise a fully differential operational amplifier (op-amp) with single-feedback loop, which reduces the mismatch between the single-ended outputs in the differential configuration. The proposed configurations are analysed in perspective of noise to achieve high accuracy with less noise and integrated with supporting circuitry. The fabricated application specific integrated circuit (ASIC) is first characterised with the internal on-chip capacitors and then integrated with micro-electro-mechanical systems (MEMS) based differential capacitive accelerometer sensor on a printed circuit board (PCB) for dynamic testing. The integrated PCB and a commercially available accelerometer (ADXL335) is mounted on a sub-woofer system and the dynamic testing is carried out. The measurement results show that the sensor interface is capable of measuring sub-fF capacitance change with zero offset less than 2 mV. The first configuration provides sensitivity of 720 mV/g, whereas the second configuration attains sensitivity of 385 mV/g. The noise floors are 400 μ g / Hz , 325 μ g / Hz , whereas the capacitance resolutions are 70 and 60 aF, respectively.

Lossless Decompression Accelerator for Embedded Processor with GUI.

The development of the mobile industry brings about the demand for high-performance embedded systems in order to meet the requirement of user-centered application. Because of the limitation of memory resource, employing compressed data is efficient for an embedded system. However, the workload for data decompression causes an extreme bottleneck to the embedded processor. One of the ways to alleviate the bottleneck is to integrate a hardware accelerator along with the processor, constructing a system-on-chip (SoC) for the embedded system. In this paper, we propose a lossless decompression accelerator for an embedded processor, which supports LZ77 decompression and static Huffman decoding for an inflate algorithm. The accelerator is implemented on a field programmable gate array (FPGA) to verify the functional suitability and fabricated in a Samsung 65 nm complementary metal oxide semiconductor (CMOS) process. The performance of the accelerator is evaluated by the Canterbury corpus benchmark and achieved throughput up to 20.7 MB/s at 50 MHz system clock frequency.

Ultra‐low power voltage reference with 40 μA maximum load current for passive sensor systems

An ultra-low power, low temperature coefficient voltage reference generator used for nanowatt-level passive sensor systems is presented. The voltage reference configuration, based on a voltage reference generating circuit embedded in the feedback loop, realises an average reference voltage (VREF) of 837.2 mV and 40 μA maximum load current. The temperature coefficient of VREF is compensated by a saturated diode-connected the positive channel Metal Oxide Semiconductor (PMOS) and a proportional to absolute temperature current. For supply voltages ranging from 0.86 to 3 V, this proposed voltage reference simulated in 55 nm a Complementary Metal Oxide Semiconductor (CMOS) process consumes an average current of 10 nA at room temperature and achieves a minimum temperature coefficient of 8.1 ppm/°C from −40°C to 125°C. The mean line sensitivity is 0.17%/V and the coefficient of variation is 2.1%.

Energy efficient neural stimulator with dynamic supply modulation

This paper reports an automatically reconfigurable series–parallel switched-capacitor step-down DC–DC converter for neural stimulation applications, fabricated with a 0.13 μm standard complementary metal oxide semiconductor process. The stimulator chip can generate pre-programmed biphasic or dynamically programmed arbitrary current waveforms, up to ±127 μA peak with 7-bit resolution. To improve the power efficiency, the supply voltages of the stimulating current sources are dynamically modulated following the output voltage. The functionality of the stimulator is verified in vitro using parylene-based microelectrode arrays in phosphate-buffered saline.

Switched-Biasing Techniques for CMOS Voltage-Controlled Oscillator.

A voltage-controlled oscillator (VCO) is a key component to generate high-speed clock of mixed-mode circuits and local oscillation signals of the frequency conversion in wired and wireless application systems. In particular, the recent evolution of new high-speed wireless systems in the millimeter-wave frequency band calls for the implementation of the VCO with high oscillation frequency and low close-in phase noise. The effect of the flicker noise on the phase noise of the VCO should be minimized because the flicker noise dramatically increases as the deep-submicron complementary metal-oxide-semiconductor (CMOS) process is scaled down, and the flicker corner frequency also increases, up to several MHz, in the up-to-date CMOS process. The flicker noise induced by the current source is a major factor affecting the phase noise of the VCO. Switched-biasing techniques have been proposed to minimize the effect of the flicker noise at the output of the VCO with biasing AC-coupled signals at the current source of the VCO. Reviewing the advantages and disadvantages reported in the previous studies, it is analyzed which topology to implement the switched-biasing technique is advantageous for improving the performance of the CMOS VCOs.

Low Phase Noise Concurrent Dual-Band (5/7 GHz) CMOS VCO Using Gate Feedback on Nonuniformly Wound Transformer

A novel low phase noise concurrent dualband complementary metal-oxide-semiconductor (CMOS) voltage-controlled oscillator (VCO) employing a gate-feedback enabled, nonuniform multiwinding transformer is proposed. The transformer consists of the wide-width looped main inductors and surrounding narrow-width looped feedback inductors, featuring a high degree of design freedom, owing to its controllable width, gap, and coupling coefficients. This novel topology enables both simultaneous and independent oscillation in two frequency bands using the main inductors with oscillation cores. In addition, the resonant tank's noise contribution can be reduced by boosting the loaded quality factor using gate-driving feedback inductors. The proposed VCO was fabricated in a 0.28-μm silicon on insulator (SOI) CMOS process. The measured results show concurrent oscillation from 4.6 to 5.6 GHz and 6.1 to 7.4 GHz with phase noise of -119.3 and -120.1 dBc/Hz at 1 MHz offset, corresponding to a figure-of-merit (FOM) of -184.4 and -185.1, whereas the FOM for low-band and high-band single-tone oscillation is -182.7 and -184.8 dBc/Hz, respectively. Finally, the FOM of the proposed VCO is compared with that of similar size concurrent dual-band VCO devices previously presented in literature.

Effect of Insertion of Dielectric Layer on the Performance of Hafnia Ferroelectric Devices

Hafnia-based ferroelectric (FE) devices have attracted significant attention as nonvolatile memory devices due to their compatibility with complementary metal–oxide–semiconductor processes. Among them, the FE tunnel junction (FTJ) has been considered as the next-generation of nonvolatile memory devices owing to its neuromorphic characteristics and nondestructive read operation as well as the high-density integration. However, degradation of ferroelectricity in a thin hafnia film causes a reduced tunneling electroresistance (TER) ratio. In this work, we inserted a TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer into the metal–FE–metal capacitor to provide an asymmetric structure for FTJ operations and recorded the enhanced remnant polarization with enhanced ferroelectricity. In this study, a high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2{P}_{r}$ </tex-math></inline-formula> value of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$44.4~\mu \text{C}$ </tex-math></inline-formula> /cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a notable TER ratio of 11.6 were observed for 6-nm thick hafnia films with 1-nm thick TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> films.

MOSFET ZTC Condition Analysis for a Self-biased Current Reference Design

In this paper a self-biased current reference based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) Zero Temperature Coefficient (ZTC) condition is proposed. It can be implemented in any Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process and provides another alternative to design current references. In order to support the circuit design, ZTC condition is analyzed using a MOSFET model that is continuous from weak to strong inversion, showing that this condition always occurs from moderate to strong inversion in any CMOS process. The proposed topology was designed in a 180 nm process, operates with a supply voltage from 1.4V to 1.8 V and occupies around 0.010mm2 of silicon area. From circuit simulations our reference showed a temperature coefficient (TC) of 15 ppm/oC from -40 to +85oC, and a fabrication process sensitivity of σ/μ = 4.5% for the current reference, including average process and local mismatch variability analysis. The simulated power supply sensitivity is estimated around 1%/V.

Research on High-Resolution Miniaturized MEMS Accelerometer Interface ASIC.

High-precision microelectromechanical system (MEMS) accelerometers have wide application in the military and civil fields. The closed-loop microaccelerometer interface circuit with switched capacitor topology has a high signal-to-noise ratio, wide bandwidth, good linearity, and easy implementation in complementary metal oxide semiconductor (CMOS) process. Aiming at the urgent need for high-precision MEMS accelerometers in geophones, we carried out relevant research on high-performance closed-loop application specific integrated circuit (ASIC) chips. According to the characteristics of the performance parameters and output signal of MEMS accelerometers used in geophones, a high-precision closed-loop interface ASIC chip based on electrostatic time-multiplexing feedback technology and proportion integration differentiation (PID) feedback control technology was designed and implemented. The interface circuit consisted of a low-noise charge-sensitive amplifier (CSA), a sampling and holding circuit, and a PID feedback circuit. We analyzed and optimized the noise characteristics of the interface circuit and used a capacitance compensation array method to eliminate misalignment of the sensitive element. The correlated double sampling (CDS) technology was used to eliminate low-frequency noise and offset of the interface circuit. The layout design and engineering batch chip were fabricated by a standard 0.35 μm CMOS process. The active area of the chip was 3.2 mm × 3 mm. We tested the performance of the accelerometer system with the following conditions: power dissipation of 7.7 mW with a 5 V power supply and noise density less than 0.5 μg/Hz1/2. The accelerometers had a sensitivity of 1.2 V/g and an input range of ±1.2 g. The nonlinearity was 0.15%, and the bias instability was about 50 μg.

Quantum Dot With a Diamond-Shaped Channel MOSFET on a Bulk Si Substrate

In this article, a p-type high- ${k}$ /metal gate (HKMG) FinFET with a special diamond-shaped channel on a bulk Si substrate for the formation of gate-induced quantum dot (QD) is reported. The electrical characteristics of the device at various temperatures and bias voltages for QD formation are extensively investigated. Remarkable oscillations in the drain current are observed for the 30-nm gate length ( ${L}_{g}$ ) transistor at ${T} =20$ K. By analyzing the experimental results as well as the simulation data obtained by TCAD, it is found that the carriers are strongly localized at the small sharp tip of the channel and the thick spacers contribute to a large confinement potential for forming QD with a large charging energy of 30 meV. This provides a promising approach for large-scale QD fabrication and integration using the mainstream bulk complementary metal oxide semiconductor (CMOS) process.