Abstract
The quality of the semiconductor–barrier interface plays a pivotal role in the demonstration of high quality reproducible quantum dots for quantum information processing. In this work, we have measured SiMOSFET Hall bars on undoped Si substrates in order to investigate the device quality. For devices fabricated in a full complementary metal oxide semiconductor (CMOS) process and of very thin oxide below a thickness of 10 nm, we report a record mobility of 17.5 × 103 cm2 V−1 s−1 indicating a high quality interface, suitable for future qubit applications. We also study the influence of gate materials on the mobilities and discuss the underlying mechanisms, giving insight into further material optimization for large scale quantum processors.
Highlights
The spin of an electron in Silicon has been considered as one of the most promising candidates for largescale quantum computers, due to its long coherence time, compactness, potential to operate at relatively high temperatures, and compatibility with CMOS technology for upscaling [1,2,3]
The quality of the semiconductor-barrier interface plays a pivotal role in the demonstration of high quality reproducible quantum dots for quantum information processing
We study the influence of gate materials on the mobilities and discuss the underlying mechanisms, giving insight into further material optimization for large scale quantum processors
Summary
During the calculation of the mobility at the lowest temperature, we observed a peak mobility higher than the KKB model (see Fig.1b) We associated this deviation to the non-linear density dependence in the small top gate voltage regime at the lowest temperature as shown in the inset of Fig.1a. This assumption is further supported because the theoretical curve can be recovered using a linear extrapolated density when calculating the mobility (see Fig.).
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