Complementary Metal Oxide Semiconductor Process Research Articles

Horizontal Current Bipolar Transistor (HCBT) Technology for High Linearity RF Mixers

The high linearity downconversion active mixers are demonstrated in the horizontal current bipolar transistor (HCBT) technology. The HCBTs fabricated by uniform n-collector doping profile, long hydrofluoric (HF) etching, and long tetramethylammonium hydroxide (TMAH) etching are shown to be optimal for mixer performance. The circuits fabricated with the optimum HCBTs in 180-nm bipolar complementary metal-oxide semiconductor (BiCMOS) process are packaged and measured, resulting in the best HCBT mixer characteristics published so far. The HCBT mixer uses a double-balanced Gilbert cell core with an integrated local oscillator (LO) buffer driver and employs an open-collector output topology. It provides broadband operation and frequency downconversion, measured up to 3 GHz, with a maximum power consumption of 550 mW at the peak linearity performance. The measured peak input third-order intercept point (IIP3) and conversion gain (CG) of 30.3 dBm and 6.0 dB, respectively (at 900-MHz input), are suitable for the base station transceivers and wireless infrastructure. The HCBT technology represents a low-cost BiCMOS platform capable of meeting the various requirements in the fabrication of the radio frequency integrated circuits (RFICs).

Simulation of High-Speed and Low-Power CMOS Binary Image Sensor Based on Gate/Body-Tied PMOSFET-Type Photodetector Using Double-Tail Comparator

In this paper, we propose a complementary metal-oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector using a double-tail comparator for highspeed and low-power operations. The GBT photodetector is based on a PMOSFET tied with a floating gate (n+ polysilicon) and a body that amplifies the photocurrent generated by incident light. A double-tail comparator compares an input signal with a reference voltage and returns the output signal as either 0 or 1. The signal processing speed and power consumption of a double-tail comparator are superior over those of conventional comparator. Further, the use of a double-sampling circuit reduces the standard deviation of the output voltages. Therefore, the proposed CMOS binary image sensor using a double-tail comparator might have advantages, such as low power consumption and high signal processing speed. The proposed CMOS binary image sensor is designed and simulated using the standard 0.18 μm CMOS process.

Development of the Backside Loading Inductive Tactile Force Sensor Using the Flip-Chip Bonding of CMOS Sensing Chip

This study presents a backside loading design inductive tactile sensor with the monolithic integration of thermometer. Based on the commercially available standard complementary metal-oxide-semiconductor (CMOS) process (the TSMC $0.35\mu \text{m}$ 2P4M CMOS process) and the in-house post CMOS processes, the sensing chip is designed and implemented. The electrical connection is further achieved by using the flip-chip bonding process, and hence the breakage of bonding wires by the tactile load can be avoided. The CMOS sensing chip consists of the magnetic sensing coil and the polysilicon RTD (resistive thermal detector). Moreover, a cavity is defined on the backside (silicon substrate) of CMOS chip to act as a mold for the polymer filler as well as the housing for the chrome steel ball contact interface. The tactile force will cause the polymer deformation and chrome steel ball displacement, and further lead to the magnetic flux change on the sensing coil. Thus, the tactile force is detected by the inductance variation of magnetic sensing coil on the CMOS chip. Moreover, the temperature variation is detected by the resistance change of RTD thermometer, and the in-situ temperature monitoring during tactile loading is achieved. The force response of the proposed tactile sensor and the temperature response of the thermometer have been characterized. The influence of temperature variation on the tactile sensor has also been calibrated. Moreover, the characteristics of the thermometer on sensing chip at different contact conditions are also investigated.

Poly-silicon light-emitting-device based electro-optical interfaces in standard silicon-CMOS integrated circuitry

A silicon-based light source using simple manufacturing process and having excellent luminous efficiency is significantly desired for the development of optoelectronic integrated circuits. In this paper, an integrated poly-silicon avalanche mode light-emitting-device (poly-SiAMLED) is fabricated using a complementary metal oxide semiconductor (CMOS) process. It utilizes the poly-silicon p-n junctions in avalanche breakdown to achieve illumination and employs the carrier injection technology to achieve about 2.9 × 10−7 external quantum efficiency and about 2.2 × 10−8 power conversion efficiency. Moreover, it is easy to fabricate because the process is compatible with the existing integrated circuit process. The proposed device can be used as one of the components of the optoelectronic interface in optoelectronic integrated circuits.

Shaping 800 nm pulses of Yb/Tm co-doped laser: A control theoretic approach

Modern literature has demonstrated the use of fluorescent probes in optical microscopy. Most recently, Ytterbium (Yb3+) and Thulium (Tm3+) doped nanocrystals have been used to achieve the imaging of single upconversion nanoparticles in the Stimulated Emission Depletion (STED) microscope. However, precise control of the stimulated emission at 800 nm caused by the discharge of the metastable 3H4 energy level of the Tm3+ acceptor probe would provide enhanced imaging in modern microscopy by suppressing visible fluorescence emitted from the focal plane. In this interdisciplinary paper, Model-Free Control is combined with Sliding Control to shape 800 nm pulsed emission of the lanthanide co-doped dual-laser system. This is achieved by controlling the stimulated emission rate via automatic adjustment of the probing laser pump power. This new type of controller will not be impacted by model errors like its model-based counterparts and can be fabricated by complementary metal oxide semiconductor (CMOS) processes paving way to photonic integration. Numerical simulation of the controller is executed and shows that the error between desired pulsed emission and the system's output was below 0.0057%. Mathematical analysis of the control technique and the results obtained from numerical simulations are presented.

6.25 GHz, 1 mV input resolution auxiliary circuit assisted comparator in 65 nm CMOS process

The need for the high-speed analogue-to-digital converters demands the use of regenerative comparators. The strong positive feedback present in the regenerative comparators helps the comparator to work efficiently at the high-speed operations. This work proposes a low power auxiliary circuit to improve the high-frequency performance of the comparator. The proposed architecture along with the conventional comparators is simulated in 65-nm complementary metal oxide semiconductor (CMOS) technology with a supply voltage of 0.9 V. The maximum operating frequency of the proposed comparator is 6.25 GHz for a differential input voltage of 1 mV.

11 Gb/s 140 GHz OOK modulator with 24.6 dB isolation utilising cascaded switch and amplifier‐based stages in 65 nm bulk CMOS

This study presents a complementary metal-oxide-semiconductor (CMOS) 140 GHz on-off-keying (OOK) modulator with high isolation and low ON-state insertion loss based on a cascaded architecture of a switch-based and amplifier-based modulators. A prototype implemented in a 65 nm bulk CMOS process operates at 140 GHz carrier input and realises 24.6 dB isolation, whereas in ON-state it achieves 0.3 dB gain and -0.2 dBm OP1 dB with 8 mW power consumption. Up to 11 Gb/s modulation is verified with the spectrum and demodulated waveform measurements. The proposed OOK modulator occupies the core area of 250×380 μm 2 .

Integrated electronics in 130 nm CMOS process for quantum key distribution sender device.

Quantum Key Distribution (QKD) is the most mature method for implementing commercial quantum communications in practice. As part of the miniaturization of practical QKD devices, an integrated electronic system in the 130 nm complementary metal oxide semiconductor process is presented for the QKD sender device. The electronics provide driving signals for the optics at the sender terminal of the quantum channel in QKD and consist mainly of three key modules, namely, a laser diode driver with a high slew rate, a high-speed physical random number generator, and a pre-driver for the electro-optic modulator. The electronic system is designed to operate at frequencies as high as 625-MHz to accommodate the frequency of the QKD system. The high degree of integration is advantageous for miniaturizing QKD sender devices.

Broadband supercontinuum generation in nitrogen-rich silicon nitride waveguides using a 300 mm industrial platform

We report supercontinuum generation in nitrogen-rich (N-rich) silicon nitride waveguides fabricated through back-end complementary-metal-oxide-semiconductor (CMOS)-compatible processes on a 300 mm platform. By pumping in the anomalous dispersion regime at a wavelength of 1200 nm, two-octave spanning spectra covering the visible and near-infrared ranges, including the O band, were obtained. Numerical calculations showed that the nonlinear index of N-rich silicon nitride is within the same order of magnitude as that of stoichiometric silicon nitride, despite the lower silicon content. N-rich silicon nitride then appears to be a promising candidate for nonlinear devices compatible with back-end CMOS processes.

360‐μW 4.1‐dB NF CMOS MedRadio receiver RF front‐end with current‐reuse Q‐boosted resistive feedback LNA for biomedical IoT applications

SummaryIn this paper, a low‐power low‐noise complementary metal‐oxide semiconductor (CMOS) receiver RF front‐end (RFFE) that employs a current‐reuse Q‐boosted resistive feedback low‐noise amplifier (RFLNA) is proposed for 401 to 406 MHz medical device radio‐communication service band IoT applications. By employing a series RLC input matching network, the proposed RFLNA has the advantages of both the conventional RFLNA and the inductively degenerated common‐source LNA without using large on‐chip spiral inductors at the sources of the main transistors. The proposed active mixer utilizes a current‐reuse transconductor, in which a p‐channel metal‐oxide semiconductor (PMOS) transistor performs a current‐bleeding function to reduce direct current (DC) and flicker noise in the switching stage of the active mixer. The proposed receiver RFFE is implemented in a 65‐nm CMOS process and achieves a voltage gain of 30.9 dB, noise figure of 4.1 dB, S11 of less than −10 dB, and IIP3 of −22.9 dBm. It operates at a supply voltage of 1 V with bias currents of 360 μA. The active die area is 0.4 mm × 0.35 mm.

Design of Signal Generators Using Active Elements Developed in I3T25 CMOS Technology Single IC Package for Illuminance to Frequency Conversion.

This paper presents a compact and simple design of adjustable triangular and square wave functional generators employing fundamental cells fabricated on a single integrated circuit (IC) package. Two solutions have electronically tunable repeating frequency. The linear adjustability of repeating frequency was verified in the range between 17 and 264 kHz. The main benefits of the proposed generator are the follows: A simple adjustment of the repeating frequency by DC bias current, Schmitt trigger (threshold voltages) setting by DC driving voltage, and output levels in hundreds of mV when the complementary metal-oxide semiconductor (CMOS) process with limited supply voltage levels is used. These generators are suitable to provide a simple conversion of illuminance to frequency of oscillation that can be employed for illuminance measurement and sensing in the agriculture applications. Experimental measurements proved that the proposed concept is usable for sensing of illuminance in the range from 1 up to 500 lx. The change of illuminance within this range causes driving of bias current between 21 and 52 μA that adjusts repeating frequency between 70 and 154 kHz with an error up to 10% between the expected and real cases.

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

A dual-frequency all-in-one Global Navigation Satellite System (GNSS) receiver with a multi-core 32-bit RISC (reduced instruction set computing) application processor was integrated and manufactured as a System-on-Chip (SoC) in a 110 nm CMOS (complementary metal-oxide semiconductor) process. The GNSS RF (radio frequency) front-end with baseband navigation engine is able to receive, simultaneously, Galileo (European Global Satellite Navigation System) E1/E5ab, GPS (US Global Positioning System) L1/L1C/L5, BeiDou (Chinese Navigation Satellite System) B1/B2, GLONASS (GLObal NAvigation Satellite System of Russian Government) L1/L3/L5, QZSS (Quasi-Zenith Satellite System development by the Japanese government) L1/L5 and IRNSS (Indian Regional Navigation Satellite System) L5, as well as all SBAS (Satellite Based Augmentation System) signals. The ability of the GNSS to detect such a broad range of signals allows for high-accuracy positioning. The whole SoC (system-on-chip), which is connected to a small passive antenna, provides precise position, velocity and time or raw GNSS data for hybridization with the IMU (inertial measurement unit) without the need for an external application processor. Additionally, user application can be executed directly in the SoC. It works in the −40 to +105 °C temperature range with a 1.5 V supply. The assembled test-chip takes 100 pins in a QFN (quad-flat no-leads) package and needs only a quartz crystal for the on-chip reference clock driver and optional SAW (surface acoustic wave) filters. The radio performance for both wideband (52 MHz) channels centered at L1/E1 and L5/E5 is NF = 2.3 dB, G = 131 dB, with 121 dBc/Hz of phase noise @ 1 MHz offset from the carrier, consumes 35 mW and occupies a 4.5 mm2 silicon area. The SoC reported in the paper is the first ever dual-frequency single-chip GNSS receiver equipped with a multi-core application microcontroller integrated with embedded flash memory for the user application program.

A Highly Linear CMOS Image Sensor Design Based on an Adaptive Nonlinear Ramp Generator and Fully Differential Pipeline Sampling Quantization with a Double Auto-Zeroing Technique

For a complementary metal-oxide-semiconductor image sensor with highly linear, low noise and high frame rate, the nonlinear correction and frame rate improvement techniques are becoming very important. The in-pixel source follower transistor and the integration capacitor on the floating diffusion node cause linearity degradation. In order to address this problem, this paper proposes an adaptive nonlinear ramp generator circuit based on dummy pixels used in single-slope analog-to-digital converter topology for a complementary metal-oxide-semiconductor (CMOS) image sensor. In the proposed approach, the traditional linear ramp generator circuit is replaced with the new proposed adaptive nonlinear ramp generator circuit that can mitigate the nonlinearity of the pixel unit circuit, especially the gain nonlinearity of the source follower transistor and the integration capacitor nonlinearity of the floating diffusion node. Moreover, in order to enhance the frame rate and address the issue of high column fixed pattern noise, a new readout scheme of fully differential pipeline sampling quantization with a double auto-zeroing technique is proposed. Compared with the conventional readout structure without a fully differential pipeline sampling quantization technique and double auto-zeroing technique, the proposed readout scheme cannot only enhance the frame rate but can also improve the consistency of the offset and delay information of different column comparators and significantly reduce the column fixed pattern noise. The proposed techniques are simulated and verified with a prototype chip fabricated using typical 180 nm CMOS process technology. The obtained measurement results demonstrate that the overall nonlinearity of the CMOS image sensor is reduced from 1.03% to 0.047%, the efficiency of the comparator is improved from 85.3% to 100%, and the column fixed pattern noise is reduced from 0.43% to 0.019%.

Speed, energy and area optimized early output quasi-delay-insensitive array multipliers.

Multiplication is a widely used arithmetic operation that is frequently encountered in micro-processing and digital signal processing. Multiplication is implemented using a multiplier, and recently, QDI asynchronous array multipliers were presented in the literature utilizing delay-insensitive double-rail data encoding and four-phase return-to-zero (RTZ) handshaking and four-phase return-to-one (RTO) handshaking. In this context, this article makes two contributions: (i) the design of a new asynchronous partial product generator, and (ii) the design of a new asynchronous half adder. We analyze the usefulness of the proposed partial product generator and the proposed half adder to efficiently realize QDI array multipliers. When the new partial product generator and half adder are used along with our indicating full adder, significant reductions are achieved in the design metrics compared to the optimum QDI array multiplier reported in the literature. The cycle time is reduced by 17%, the area is reduced by 16.1%, the power is reduced by 15.3%, and the product of power and cycle time is reduced by 29.6% with respect to RTZ handshaking. On the other hand, the cycle time is reduced by 13%, the area is reduced by 16.1%, the power is reduced by 15.2%, and the product of power and cycle time is reduced by 26.1% with respect to RTO handshaking. Further, the RTO handshaking is found to be preferable to RTZ handshaking to achieve slightly improved optimizations in the design metrics. The QDI array multipliers were realized using a 32/28nm complementary metal oxide semiconductor (CMOS) process technology.

A CMOS-Thyristor Based Temperature Sensor with +0.37 °C/-0.32 °C Inaccuracy.

This paper describes a voltage controlled oscillator (VCO) based temperature sensor. The VCOs are composed of complementary metal–oxide–semiconductor (CMOS) thyristor with the advantage of low power consumption. The period of the VCO is temperature dependent and is function of the transistors’ threshold voltage and bias current. To obtain linear temperature characteristics, this paper constructed the period ratio between two different-type VCOs. The period ratio is independent of the temperature characteristics from current source, which makes the bias current generator simplified. The temperature sensor was designed in 130 nm CMOS process and it occupies an active area of 0.06 mm2. Based on the post-layout simulation results, after a first-order fit, the sensor achieves an inaccuracy of +0.37/−0.32 °C from 0 °C to 80 °C, while the average power consumption of the sensor at room temperature is 156 nW.

Reliability Modelling and Prediction Method for Phase Change Memory Using Optimal Pulse Conditions

Phase change memory (PCM) has reached the level of mass production. The first step in mass production is determining the proper pulse conditions of high-resistance (HR) and low-resistance (LR) states to realize the best performance of PCM chips on the basis of longer endurance characteristics. However, due to the neglect of each of the relations as well as the square term of each relationship for pulse conditions, the standard screening method for pulse conditions cannot accurately determine the optimal pulse conditions. A new statistical prediction method based on regression analysis is presented in this work. The method can model and predict the optimal pulse conditions of PCM chips on the basis of longer endurance characteristics. In the method, the parameter estimates, model equations and surface plot are generated by the least-mean-square (LMS) method for the regression analysis; the prediction model is established by monitoring the distributions of the resistance values collected from a 4 Kbit block of the 4Mbit PCM test chips in 40 nm complementary metal oxide semiconductor (CMOS) process.

A wirelessly powered low‐power digital temperature sensor

SummaryA wirelessly powered temperature sensor is presented in complementary metal‐oxide‐semiconductor (CMOS) 180‐nm process. The wireless power transfer (WPT) is performed using resonant magnetic coupling, and a diode‐less AC to DC conversion is achieved through a quadrature‐oscillator with native‐MOS. The quadrature‐signals are subsequently used to control the diode‐less rectifier switches. The on‐chip temperature sensor exploits the subthreshold region temperature, and the sensed temperature is converted to frequency using a ring‐oscillator, which is implemented using differential cross coupled oscillator‐based delay cells. The temperature sensor architecture also employs a temperature‐insensitive replica circuit to minimize process dependence and enhance power‐supply rejection ratio (PSRR) of the sensing process. The application‐specific integrated circuit has been designed and fabricated in 180‐nm CMOS process and has dimensions of 2 mm × 2 mm. The measurement results demonstrate that the WPT circuit generates a DC voltage of 1V with a power transfer efficiency of 85% for distances 2 to 8 mm with settling time of microseconds to milliseconds. The temperature sensor demonstrates a resolution of < ±0.6C with a sensitivity of 0.52 mV/C and 126.9 Hz/C along with PSRR of −63dB and Integral Non‐Linraity (INL) of 5% measured across six different dies. The back‐scattering communication demonstrates a −53‐dB signal at a distance of 4 mm without affecting the WPT efficiency. The total power consumption of the temperature sensor along with the integrated biases is 120 nW.

Low-Concentration Ammonia Gas Sensors Manufactured Using the CMOS-MEMS Technique.

This study describes the fabrication of an ammonia gas sensor (AGS) using a complementary metal oxide semiconductor (CMOS)–microelectromechanical system (MEMS) technique. The structure of the AGS features interdigitated electrodes (IDEs) and a sensing material on a silicon substrate. The IDEs are the stacked aluminum layers that are made using the CMOS process. The sensing material; polypyrrole/reduced graphene oxide (PPy/RGO), is synthesized using the oxidation–reduction method; and the material is characterized using an electron spectroscope for chemical analysis (ESCA), a scanning electron microscope (SEM), and high-resolution X-ray diffraction (XRD). After the CMOS process; the AGS needs post-processing to etch an oxide layer and to deposit the sensing material. The resistance of the AGS changes when it is exposed to ammonia. A non-inverting amplifier circuit converts the resistance of the AGS into a voltage signal. The AGS operates at room temperature. Experiments show that the AGS response is 4.5% at a concentration of 1 ppm NH3; and it exhibits good repeatability. The lowest concentration that the AGS can detect is 0.1 ppm NH3

A Stacked Back Side-Illuminated Voltage Domain Global Shutter CMOS Image Sensor with a 4.0 μm Multiple Gain Readout Pixel †.

A backside-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor with 4.0 μm voltage domain global shutter (GS) pixels has been fabricated in a 45 nm/65 nm stacked CMOS process as a proof-of-concept vehicle. The pixel components for the photon-to-voltage conversion are formed on the top substrate (the first layer). Each voltage signal from the first layer pixel is stored in the sample-and-hold capacitors on the bottom substrate (the second layer) via micro-bump interconnection to achieve a voltage domain GS function. The two sets of voltage domain storage capacitor per pixel enable a multiple gain readout to realize single exposure high dynamic range (SEHDR) in the GS operation. As a result, an 80dB SEHDR GS operation without rolling shutter distortions and motion artifacts has been achieved. Additionally, less than −140dB parasitic light sensitivity, small noise floor, high sensitivity and good angular response have been achieved.

Photon-Detection-Probability Simulation Method for CMOS Single-Photon Avalanche Diodes.

Single-photon avalanche diodes (SPADs) in complementary metal-oxide-semiconductor (CMOS) technology have excellent timing resolution and are capable to detect single photons. The most important indicator for its sensitivity, photon-detection probability (PDP), defines the probability of a successful detection for a single incident photon. To optimize PDP is a cost- and time-consuming task due to the complicated and expensive CMOS process. In this work, we have developed a simulation procedure to predict the PDP without any fitting parameter. With the given process parameters, our method combines the process, the electrical, and the optical simulations in commercially available software and the calculation of breakdown trigger probability. The simulation results have been compared with the experimental data conducted in an 800-nm CMOS technology and obtained a good consistence at the wavelength longer than 600 nm. The possible reasons for the disagreement at the short wavelength have been discussed. Our work provides an effective way to optimize the PDP of a SPAD prior to its fabrication.