Abstract
Multiplication is a widely used arithmetic operation that is frequently encountered in micro-processing and digital signal processing. Multiplication is implemented using a multiplier, and recently, QDI asynchronous array multipliers were presented in the literature utilizing delay-insensitive double-rail data encoding and four-phase return-to-zero (RTZ) handshaking and four-phase return-to-one (RTO) handshaking. In this context, this article makes two contributions: (i) the design of a new asynchronous partial product generator, and (ii) the design of a new asynchronous half adder. We analyze the usefulness of the proposed partial product generator and the proposed half adder to efficiently realize QDI array multipliers. When the new partial product generator and half adder are used along with our indicating full adder, significant reductions are achieved in the design metrics compared to the optimum QDI array multiplier reported in the literature. The cycle time is reduced by 17%, the area is reduced by 16.1%, the power is reduced by 15.3%, and the product of power and cycle time is reduced by 29.6% with respect to RTZ handshaking. On the other hand, the cycle time is reduced by 13%, the area is reduced by 16.1%, the power is reduced by 15.2%, and the product of power and cycle time is reduced by 26.1% with respect to RTO handshaking. Further, the RTO handshaking is found to be preferable to RTZ handshaking to achieve slightly improved optimizations in the design metrics. The QDI array multipliers were realized using a 32/28nm complementary metal oxide semiconductor (CMOS) process technology.
Highlights
Multiplication is a fundamental arithmetic operation that is frequented in micro-processing and digital signal processing
To make a straightforward comparison with the early output QDI array multiplier whose architecture is portrayed by Fig 5B, we considered realizing Fig 8 using the proposed partial product generator (i.e., Fig 3A and 3B), the early output full adder of [51], and the early output half adder depicted by Fig 9
QDI array multipliers corresponding to the architectures shown in Fig 5B and Fig 8 were physically realized based on RTZ and RTO handshaking using a 32/28 nm complementary metal oxide semiconductor (CMOS) process [26]
Summary
Multiplication is a fundamental arithmetic operation that is frequented in micro-processing and digital signal processing. Metku et al [14] custom-realized 4×4 QDI array multipliers using NCL gates which were designed using static CMOS and gate diffusion input (GDI) [24,25] techniques They observed that the GDI design style results in reduced area and less average power compared to the static CMOS implementation. A digital logic circuit cannot be constructed using just the C-element and the inverter This necessitated the introduction and assumption of isochronic forks [17] as the weakest possible compromise to delay-insensitivity. The problem with realizing a QDI array multiplier using only early output building blocks such as half adders and full adders and partial product generators is discussed, and a solution for the same is given.
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