Abstract
This paper presents a 10-bit 0.909-MHz 8-channel dual-mode successive approximation (SAR) analogue-to-digital converter (ADC) for brushless direct current (BLDC) motor drive, using a Taiwan Semiconductor Manufacturing (TSMC) 0.25 μm 1P3M Complementary Metal Oxide Semiconductor (CMOS) process. The sample-and-hold (S/H) circuit operates with two sampling modes. One is individually sampling eight channels in sequence with an S/H circuit and the other is sampling four channels simultaneously with four S/H circuits. All sampled data will be digitized with high-speed SAR ADC in time division multiplexing (TDM). A dynamic latch-type comparator is utilized to latch the output at an upper or lower level. The advantage of the designed comparator is that it performs with positive feedback to quickly complete the latch function. The double-tail latch-type architecture is utilized to mitigate the significant kickback effect by separating the pre-amplifier stage from the latch. By integrating an input NMOSFET with an input PMOSFET, the designed latch-type comparator can perform with full-swing input voltage. Measurements show that the signal-to-noise ratio (SNR), signal-to-noise-and-distortion ratio (SNDR), effective number of bits (ENOB), power consumption, and chip area are 50.56 dB, 57.03 dB, 8.11 bits, 833 μW, and 1.35 × 0.98 mm2, respectively. The main advantages of the proposed multichannel dual-mode SAR ADC are its low power consumption of 833 μW and high measured resolution of 8.11 bits.
Highlights
This paper proposed a 10-bit 2.27 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with two sampling modes and an eight-channel switch, which is usually used in the brushless direct current (BLDC) motor
We proposed a 10-bit 0.909-MHz 8-channel dual-mode SAR ADC for BLDC motor drive
The proposed sample and hold circuit is made of a sampling capacitor and a simple NMOSFET driven by the boosted driver to achieve both low power and wide bandwidth
Summary
This paper proposed a 10-bit 2.27 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with two sampling modes and an eight-channel switch, which is usually used in the brushless direct current (BLDC) motor. The field programmable gate array (FPGA)-based new digital pulse-width modulation (PWM) controller results in a considerable reduction of size and the cost of the system for BLDC motor drive [1]. The optical sensor can be used to measure the rotation speed of BLDC motor using the pulse width modulation (PWM) and the serial interface can be implemented using an energy-effective eight-bit SAR ADC [2]. To improve the performance of BLDC motor, integrating the ADC with control circuits is a good idea for electric vehicle, especially for high-voltage process. This idea had been published in [3] by integrating the permanent-magnet synchronous motor (PMSM) with a 10-bit SAR ADC.
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