Abstract
A novel radix-4 Booth encoding scheme has been presented in this paper. By means of the modified truth table, the transistor level delay from inputs to the partial products has been reduced to four transistors. Also, the output waveforms are free of glitch due to the utilization of pass-transistor logic. The calculation of propagation delay for the critical path has been provided to show the superior speed performance of the proposed architecture. Based on the simulation results using HSPICE for Taiwan semiconductor manufacturing company 0.18 µm standard complementary metal–oxide–semiconductor process and 1.8 V power supply, a speed improvement of 24% is obtained compared to the previous architectures when the proposed scheme along with the best reported works have been redesigned and simulated in the same technology platform.
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Schedule a callMore From: Proceedings of the National Academy of Sciences, India Section A: Physical Sciences
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