Complementary Field Effect Transistors Research Articles

CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling

This article explores and evaluates six-transistor static random access memory (SRAM) bitcell design options for sequential and monolithic complementary field-effect transistors (CFET) in 5-Å-compatible (A5) and 3-Å-compatible (A3) technology. A5 CFET offers up to 55% and 40% SRAM bitcell area scaling due to stacked architecture as compared to 14-Å-compatible (A14) nanosheet (NS) technology and 10-Å-compatible (A10) forksheet (FS) technology counterparts, respectively. A dielectric isolation wall (DIW) between gates is introduced in A3 CFET SRAM as a scaling booster. Replacement of gate-cuts with DIW results in up to 17% bitcell area scaling in A3 as compared to A5 CFET SRAM. However, aggressive area scaling introduces routing complexity and limits the node-to-node power and performance (PP) gain. Thus, the interconnect design guidelines are provided to overcome these challenges for power, performance, and area (PPA) enhancements of high-density (HD) SRAM.

Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process

Complementary field-effect transistor (CFET) is a future transistor type with a high potential to be used beyond 3-nm technology nodes. Despite its high future value, studies related to CFETs mostly focused on the device aspects. In other words, the path of CFET full-chip IC design is not fully demystified, knowing that various design factors/steps (such as schematic, layout, parasitics, design flow) must be considered on top of device traits for full-chip level IC. Therefore, this study focuses on enlightening the remaining factors/steps for full-chip IC design. In detail, we notify the importance of parasitics from various aspects of CFET design and provide optimization solutions. Compared to nanosheet FET (NSFET) on the full-chip scale, CFET shows a reduction of the area by −48.2%, power by −29.4%, total wirelength by −32.5%, and the number of cells by −18.1%.

A 211-to-263-GHz Dual-LC-Tank-Based Broadband Power Amplifier With 14.7-dBm P SAT and 16.4-dB Peak Gain in 130-nm SiGe BiCMOS

This article presents a broadband sub-terahertz (THz) power amplifier (PA) with a low-loss four-way power combiner. The proposed power combiner consists of an improved zero-degree combiner (ZDC) and a three-conductor Marchand balun simultaneously achieving broadband matching and power combining. The proposed three-conductor Marchand balun adopts a dual- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LC$ </tex-math></inline-formula> tank technique by merging two resonators, and it can be equivalent to a transformer-based multi-resonating network. The power distribution is realized by one input power splitter generating two pairs of differential signals and two parallel 1-to-2 active power splitters. This hybrid distribution driving network further enhances efficiency and power gain. Based on these improvements, a high-output-power sub-THz PA with superior efficiency has been fabricated in the 130-nm SiGe bipolar complementary metal oxide silicon field effect transistor (BiCMOS) technology. The three-stage PA achieves a peak power gain of 16.4 dB, 3-dB small-signal gain bandwidth of 52 GHz from 211 to 263 GHz, a measured maximum saturated output power of 14.7 dBm at 224 GHz, and a peak power-added efficiency (PAE) of 3.13% at 220 GHz. The folded input splitter and extremely compact power combining methodology lead to a core area of 770 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}\,\,\times \,\,280\,\,\mu \text{m}$ </tex-math></inline-formula> .

Heterogeneous Integration of Atomically-Thin Indium Tungsten Oxide Transistors for Low-Power 3D Monolithic Complementary Inverter.

In this work, the authors demonstrate a novel vertically-stacked thin film transistor (TFT) architecture for heterogeneously complementary inverter applications, composed of p-channel polycrystalline silicon (poly-Si) and n-channel amorphous indium tungsten oxide (a-IWO), with a low footprint than planar structure. The a-IWO TFT with channel thickness of approximately 3-4 atomic layers exhibits high mobility of 24 cm2 V-1 s-1 , near ideally subthreshold swing of 63mV dec-1 , low leakage current below 10-13 A, high on/off current ratio of larger than 109 , extremely small hysteresis of 0mV, low contact resistance of 0.44 kΩ-µm, and high stability after encapsulating a passivation layer. The electrical characteristics of n-channel a-IWO TFT are well-matched with p-channel poly-Si TFT for superior complementary metal-oxide-semiconductor technology applications. The inverter can exhibit a high voltage gain of 152V V-1 at low supply voltage of 1.5V. The noise margin can be up to 80% of supply voltage and perform the symmetrical window. The pico-watt static power consumption inverter is achieved by the wide energy bandgap of a-IWO channel and atomically-thin channel. The vertically-stacked complementary field-effect transistors (CFET) with high energy-efficiency can increase the circuit density in a chip to conform the development of next-generation semiconductor technology.

Application of long short-term memory modeling technique to predict process variation effects of stacked gate-all-around Si nanosheet complementary-field effect transistors

Emerging machine-learning (ML) methodology has been overcoming the challenging task of analyzing the process variation effect of nanoscale devices using 3-D stochastic device simulation. In this study, the effects of process variations on the electrical characteristics of the stacked gate all around (GAA) silicon nanosheet (NS) complementary field effect transistors (CFETs) are predicted using long short-term memory (LSTM) based ML model. The LSTM algorithm is less time-consuming and computationally effective as compared to conventional device modeling tools. For this work, a two-channel stacked CFET, formed by folding n-FET on top of p-FET, is considered. We utilize six important process parameters as input features to the LSTM model and estimate the variations in key electrical characteristics, such as threshold voltage (VTH), off-current (IOFF), on-current (ION), subthreshold slope (SS), and drain induced barrier lowering (DIBL). To avoid overfitting in the training phase, an early stopping regularization technique is applied to construct a high-performance LSTM model. In addition, to compare the predictive performance of our proposed ML-based LSTM model, the baseline MLP (multi-layer perceptrons) model is implemented. The results of this study show that the LSTM model with an r2-score > 95% outperforms the baseline model which has r2-score < 75%. Furthermore, the estimated rmse of LSTM in an order of 10−7 is 10 times lower than that of the baseline model whose rmse is in an order of 10−6.

Heterogeneous complementary field-effect transistors based on silicon and molybdenum disulfide

Heterogeneous complementary field-effect transistors based on silicon and molybdenum disulfide

Large‐Scale Ultrathin Channel Nanosheet‐Stacked CFET Based on CVD 1L MoS2/WSe2

AbstractNanosheet (NS) vertical‐stacked complementary field‐effect transistors (CFETs), where the NS n‐FET and NS p‐FET are vertically stacked and controlled using a common gate, would result in maximum device footprint reduction. However, silicon‐based transistor will become invalid due to mobility degradation and leakage current rising when scaling the thickness of channel and dielectric. Here, it is experimentally demonstrated that CFET can scaling down to 1 nm channel thickness with excellent performance, where chemical vapor deposition (CVD) one layer (1L) WSe2p‐type NS FET is vertically stacked on top of CVD 1L MoS2n‐type NS FET. Bottom MoS2NS FET achieves high on‐state current ofION = 3.3 × 10−5A µm µm−1and low off‐state current ofIOFF = 3.3 × 10−13A µm µm−1atVDS = 0.7 V, with the subthreshold swing reaching 80 mV dec−1. Top WSe2NS FET achieves high on‐state current ofION = 1.2 × 10−5A µm µm−1andIOFF = 4 × 10−11A µm µm−1atVDS = −0.7 V, while the subthreshold swing reaching 150 mV dec−1. Statistical data of 22 CFET devices demonstrate excellent uniformity toward large‐area applications. The CFET based on large‐scale 2D materials breaks the limit of channel scaling and provides a technological base for future high‐performance and low‐power electronics.

Threshold Voltage Adjustment by Varying Ge Content in SiGe p-Channel for Single Metal Shared Gate Complementary FET (CFET).

We have demonstrated the method of threshold voltage (VT) adjustment by controlling Ge content in the SiGe p-channel of N1 complementary field-effect transistor (CFET) for conquering the work function metal (WFM) filling issue on highly scaled MOSFET. Single WFM shared gate N1 CFET was used to study and emphasize the VT tunability of the proposed Ge content method. The result reveals that the Ge mole fraction influences VTP of 5 mV/Ge%, and a close result can also be obtained from the energy band configuration of Si1-xGex. Additionally, the single WFM shared gate N1 CFET inverter with VT adjusted by the Ge content method presents a well-designed voltage transfer curve, and its inverter transient response is also presented. Furthermore, the designed CFET inverter is used to construct a well-behaved 6T-SRAM with a large SNM of ~120 mV at VDD of 0.5 V.

Design of joint reconfigurable hybrid adder and subtractor using FinFET and GnrFET technologies

Many applications, such as integrated circuit based digital signal processors (DSPs) and arithmetic logical units (ALUs), rely on adders and subtractors, which are fundamental blocks. Traditional adders and subtractors were created using complementary metal oxide semi-conductor (CMOS) and field effect transistor (FET) technologies, which have increased the number of transistors, path delays, and power consumption. Therefore, this article focuses on the implementation of hybrid adders and subtractors utilizing FinFET and graphene nano-ribbon FET (GnrFET) based nanotechnologies. Initially, a multiplexer logic-based carry output predictable full adder (COPFA) is developed with a fast selection of carry-outputs, which significantly reduces the delays generated in sum estimation. Then, a path selectable reconfigurable hybrid adder (PSRHA) is developed by selecting the high-speed and low-speed carry propagation paths through the COPFA module. Further, a path selectable reconfigurable hybrid subtractor (PSRHS) also developed using two-complement PSRHA addition. Finally, a single architecture for both addition and subtraction are achieved through a joint reconfigurable hybrid adder and subtractor (JRHAS). From the simulations, the COPFA module resulted in a propagation delay (PD) of 7.2792 ns, static power consumption (SPC) of 2.4369nw, and total energy consumption (TEC) of 0.9077 nJ, while the PSRHA module resulted in PD of 2.45317 ns, SPC of 2.55681nw, TEC of 0.0912 nJ. In addition, the PSRHS module resulted in PD as 2.5297 ns, SPC as 2.8428nw, TEC as 0.0662 nJ, and the JRHAS module resulted in PD as 17.178 ns, SPC as 5.4036nw, TEC as 2.0543 nJ. Overall simulations revealed that the proposed COPFA, PSRHA, PSRHS, and JRHAS resulted in optimal performance as compared to conventional methods in terms of power, delay, and energy metrics.

Cryogenic Quasi-Ballistic Transport Enhanced by Strained Silicon Technologies in 14-nm Complementary Fin Field Effect Transistors Through Virtual Source Model

Cryogenic Quasi-Ballistic Transport Enhanced by Strained Silicon Technologies in 14-nm Complementary Fin Field Effect Transistors Through Virtual Source Model

ОСОБЕННОСТИ СХЕМОТЕХНИКИ ОПЕРАЦИОННЫХ УСИЛИТЕЛЕЙ НА КОМПЛЕМЕНТАРНЫХ ПОЛЕВЫХ ТРАНЗИСТОРАХ С УПРАВЛЯЮЩИМ PN-ПЕРЕХОДОМ

The systematic component of the offset voltage (Voff) of two-stage BJT and CMOS operationalamplifiers (Op-Amps) with classical architecture significantly depends on the numericalvalues (difference from unity) of the current transfer coefficient (Ki≈1) of the current mirrors (CM)used. This parameter of CM is also influenced by the Earley stress of their dominant active components.Current JFET mirrors are today a weak link in modern JFET analog circuitry and theyare impractical to use in the structure of JFET Op-Amps. The article posed and solved the problemof the conditions for the elimination of CM in an Op-Amps based on field-effect transistorswith a control pn-junction for the case when it is necessary to obtain a small Voff. Variants of practicalcircuits of input (InS) and intermediate (IntS) stages of microelectronic operational amplifiersbased on complementary field-effect transistors with a control pn-junction (CJFET) are proposed.Their main feature is the absence of a current mirror, which, when implemented on aCJFET, negatively affects the main parameters of the Op-Amps in terms of the systematic componentof the offset voltage, the attenuation coefficients of the input common-mode signal, and thesuppression of noise on the power buses. In this regard, InSs and IntSs circuits are promising,which do not use this CJFET functional unit. The circuits of Op-Amps based on the developed InSswith an open gain of more than 80 dB and a systematic component of the offset voltage within 300μV with low current consumption in a static mode are presented. The relevance of the performedstudies lies in the need to develop the theory of designing high-precision JFET and CJFET IPmodulesfor use in structures of low-noise analog interfaces of sensors of various physical quantities,including those operating in severe operating conditions (exposure to low temperatures andradiation) The proposed circuits can be implemented on wide-gap semiconductors (SiC JFET,GaN JFET or GaAs JFET).

Wafer-Scale Demonstration of MBC-FET and C-FET Arrays Based on Two-Dimensional Semiconductors.

Two-dimentional semiconductors have shown potential applications in multi-bridge channel field-effect transistors (MBC-FETs) and complementary field-effect transistors (C-FETs) due to their atomic thickness, stackability, and excellent electrical properties. However, the exploration of MBC-FET and C-FET based on large-scale 2D semiconductors is still lacking. Here, based on a reliable vertical stacking of wafer-scale 2D semiconductors, large-scale MBC-FETs and C-FETs using n-type MoS2 and p-type MoTe2 are successfully fabricated. The drive current of an MBC-FET with two layers of MoS2 channel (20µm/10µm) is up to 60µA under 1V bias. Compared with the single-gate MoS2 FET, the carrier mobility of MBC-FET is 2.3 times higher and the sub-threshold swing is 70% smaller. Furthermore, NAND and NOR logic circuits are also constructed based on two vertically stacked MoS2 channels. Then, C-FET arrays are fabricated by 3D integrating n-type MoS2 FET and p-type MoTe2 FET, which exhibit a voltage gain of 7V/V when VDD = 4V. In addition, this C-FET device can directly convert light signals to an electrical digital signal within a single device. The demonstration of MBC-FET and C-FET based on large-scale 2D semiconductors will promote the application of 2D semiconductors in next-generation circuits.

First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications

In this article, heterogeneous complementary field-effect-transistor (CFET) constructed by vertically stacking amorphous indium gallium zinc oxide (a-IGZO) n-channel on poly-Si p-channel with their own dielectric layer and work function metal gate inverters were demonstrated. Meanwhile, high-frequency IGZO radio frequency (RF) devices with poly-Si as guard ring material simultaneously were fabricated in the same process. High <inline-formula> <tex-math notation="LaTeX">${f}_{\text {T}}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">${f}_{\text {max}}$ </tex-math></inline-formula> IGZO Radio Frequency Integrated Circuits (RFICs) with the excellent on&#x2013;off ratio need to be promoted by introducing fluorine-based gas. For the IGZO device in CFET, its threshold voltage can be tuned by the adjusted gate for ideal inverter operation at different supply voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{\text {DD}}$ </tex-math></inline-formula>). Moreover, the swing of the IGZO transistor and the gain extracted from voltage transfer characteristic (VTC) curves can also be improved when the controlled gate and adjusted gate are connected as an input terminal, but the <inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> tunability for the inverter is satisfied in the meantime. We also simulated 6T-SRAM circuit by SPICE model to further investigate the potential of an adjusted gate for optimizing the noise margin during SRAM operation.

An enhanced two-dimensional hole gas (2DHG) C\u2013H diamond with positive surface charge model for advanced normally-off MOSFET devices

Though the complementary power field effect transistors (FETs), e.g., metal–oxide–semiconductor-FETs (MOSFETs) based on wide bandgap materials, enable low switching losses and on-resistance, p-channel FETs are not feasible in any wide bandgap material other than diamond. In this paper, we propose the first work to investigate the impact of fixed positive surface charge density on achieving normally-off and controlling threshold voltage operation obtained on p-channel two-dimensional hole gas (2DHG) hydrogen-terminated (C-H) diamond FET using nitrogen doping in the diamond substrate. In general, a p-channel diamond MOSFET demonstrates the normally-on operation, but the normally-off operation is also a critical requirement of the feasible electronic power devices in terms of safety operation. The characteristics of the C–H diamond MOSFET have been analyzed with the two demonstrated charge sheet models using the two-dimensional Silvaco Atlas TCAD. It shows that the fixed-Fermi level in the bulk diamond is 1.7 eV (donor level) from the conduction band minimum. However, the upward band bending has been obtained at Al2O3/SiO2/C-H diamond interface indicating the presence of inversion layer without gate voltage. The fixed negative charge model exhibits a strong inversion layer for normally-on FET operation, while the fixed positive charge model shows a weak inversion for normally-off operation. The maximum current density of a fixed positive interface charge model of the Al2O3/C-H diamond device is − 290 mA/mm, which corresponds to that of expermental result of Al2O3/SiO2/C-H diamond − 305 mA/mm at a gate-source voltage of − 40 V. Also, the threshold voltage Vth is relatively high at Vth = − 3.5 V, i.e., the positive charge model can reproduce the normally-off operation. Moreover, we also demonstrate that the Vth and transconductance gm correspond to those of the experimental work.

Analytical Model of CFET Parasitic Capacitance for Advanced Technology Nodes

The complementary field-effect transistor (CFET) with stacked N-type FET (NFET) and P-type FET (PFET) is an attractive approach to shrink the footprint of multiple devices at circuit level and increase transistor density. Compared with traditional device structure, the unique geometry of CFET brings very different parasitics. In this work, we take the inverter as an exemplar CFET circuit building block and provide analytical compact models of calculating parasitic capacitance, which is critical to enable fast and accurate simulations at circuit level. The validity of the models is calibrated and verified with 3-D numerical simulations. A comparison between the CFET inverter with its same ground-rule gate-all-around FET (GAAFET) counterpart reveals the critical CFET design parameters and demonstrates performance advantage of CFET architecture.

Design of JL-CFET (junctionless complementary field effect transistor)-based inverter for low power applications

Junctionless complementary field effect transistor (JL-CFET) is an emerging device that needs a small layout area and low fabrication cost. However, in order for the JL-CFET to be adopted for low power applications, two main constraints need to be overcome: (a) a high work function of metal gate and (b) a low drain current. In this work, an optimal device design is proposed to overcome those problems, by analyzing various performance metrics, such as on-state drive current, subthreshold swing, drain induced barrier lowering, propagation delay time, and ring oscillator’s oscillation frequency, which are extracted from various structures of JL-CFET. In addition, the negative capacitance effect in JL-CFET is examined to address the limit from device structures.

Complementary Two-Dimensional (2-D) FET Technology With MoS2/hBN/Graphene Stack

This paper demonstrates a complementary 2-D field-effect transistor (FET) technology with molybdenum disulfide (MoS2) as the active film, hexagonal boron nitride (hBN) as the gate dielectric, and graphene as the gate electrode. The active region of the n-channel (n-FET) and p-channel (p-FET) devices are formed by undoped and Nb-doped MoS2, respectively. The complementary FETs have the desirable threshold voltage polarity, similar current drive, and high on-off current ratios of more than 106. A complementary metal-oxidesemiconductor (CMOS) inverter has been fabricated and the measured gain is about 14 with 90% noise margin at a 2 V power supply.

2.4-GHz Highly Selective IoT Receiver Front End With Power Optimized LNTA, Frequency Divider, and Baseband Analog FIR Filter

High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4-GHz industrial, scientific, and medical (ISM)-band. In addition, low power consumption is very important for Internet-of-Things (IoT) receivers. We propose a 2.4-GHz zero-intermediate frequency (IF) receiver front-end architecture that reduces power consumption by 2 × compared with state-of-the-art and improves selectivity by >20-dB without compromising on other receiver metrics. To achieve this, the entire receive chain is optimized. The low-noise transconductance amplifier (LNTA) is optimized to combine low noise with low power consumption. State-of-the-art sub-30-nm complementary metal-oxide-semiconductor (CMOS) processes have almost equal strength complementary field-effect transistors (FETs) that result in altered design tradeoffs. A Windmill 25%-duty cycle frequency divider architecture is proposed, which uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2 dB or more reduced phase noise when benchmarked against state-of-the-art designs. An analog finite impulse response (FIR) filter is implemented to provide very high receiver selectivity with ultralow power consumption. The receiver front end is fabricated in a 22-nm fully depleted silicon-on-insulator (FDSOI) technology and has an active area of 0.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It consumes 370 μW from a 700-mV supply voltage. This low power consumption is combined with a 5.5-dB noise figure. The receiver front end has -7.5-dBm input-referred third-order-intercept point (IIP3) and 1-dB gain compression for a -22-dBm blocker, both at maximum gain of 61 dB. From three channels offset onward, the adjacent channel rejection (ACR) is ≥63 dB for Bluetooth Low-Energy (BLE), BT5.0, and IEEE802.15.4.

Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters

In this study, conventional CMOS and complementary field-effect transistor (CFET) inverters based on a vertically stacked-nanosheet (NS) structure were fabricated. The NS below 8-nm channel layer thickness ( ${T}_{{\text {Si}}}$ ) was obtained by dry etching and wet etching processes. The channel thickness is controlled by dry etching, and the channel width was shrunk down by wet etching. Compared to single nanowire field-effect transistors (NSFETs), stacked NSFETs exhibit higher ON-current performance. For the CMOS inverter, the voltage transfer characteristics (VTCs) could be matched much better by adjusting the channel widths and layers for N-channel MOSFET (NFET) and P-channel MOSFET (PFET), respectively. For the CFET inverter, layout areas could be reduced and requires less number of lithographic and ion implantation steps contrary to the CMOS inverter. However, we observe that the VTCs of the CFET inverters still show asymmetric behavior due to the difficulties of adjustment in NS layers and systematic behavior of threshold voltages for NFETs/PFETs. This work experimentally demonstrates the CMOS and CFET inverters on the vertically stacked NS structure, which is promising for system-on-panel (SoP) and 3-D-ICs applications.

Chirality-Enriched Carbon Nanotubes for Next-Generation Computing.

For the past half century, silicon has served as the primary material platform for integrated circuit technology. However, the recent proliferation of nontraditional electronics, such as wearables, embedded systems, and low-power portable devices, has led to increasingly complex mechanical and electrical performance requirements. Among emerging electronic materials, single-walled carbon nanotubes (SWCNTs) are promising candidates for next-generation computing as a result of their superlative electrical, optical, and mechanical properties. Moreover, their chirality-dependent properties enable a wide range of emerging electronic applications including sub-10 nm complementary field-effect transistors, optoelectronic integrated circuits, and enantiomer-recognition sensors. Here, recent progress in SWCNT-based computing devices is reviewed, with an emphasis on the relationship between chirality enrichment and electronic functionality. In particular, after highlighting chirality-dependent SWCNT properties and chirality enrichment methods, the range of computing applications that have been demonstrated using chirality-enriched SWCNTs are summarized. By identifying remaining challenges and opportunities, this work provides a roadmap for next-generation SWCNT-based computing.