Application of long short-term memory modeling technique to predict process variation effects of stacked gate-all-around Si nanosheet complementary-field effect transistors

Abstract

Emerging machine-learning (ML) methodology has been overcoming the challenging task of analyzing the process variation effect of nanoscale devices using 3-D stochastic device simulation. In this study, the effects of process variations on the electrical characteristics of the stacked gate all around (GAA) silicon nanosheet (NS) complementary field effect transistors (CFETs) are predicted using long short-term memory (LSTM) based ML model. The LSTM algorithm is less time-consuming and computationally effective as compared to conventional device modeling tools. For this work, a two-channel stacked CFET, formed by folding n-FET on top of p-FET, is considered. We utilize six important process parameters as input features to the LSTM model and estimate the variations in key electrical characteristics, such as threshold voltage (VTH), off-current (IOFF), on-current (ION), subthreshold slope (SS), and drain induced barrier lowering (DIBL). To avoid overfitting in the training phase, an early stopping regularization technique is applied to construct a high-performance LSTM model. In addition, to compare the predictive performance of our proposed ML-based LSTM model, the baseline MLP (multi-layer perceptrons) model is implemented. The results of this study show that the LSTM model with an r2-score > 95% outperforms the baseline model which has r2-score < 75%. Furthermore, the estimated rmse of LSTM in an order of 10−7 is 10 times lower than that of the baseline model whose rmse is in an order of 10−6.