Design of joint reconfigurable hybrid adder and subtractor using FinFET and GnrFET technologies

Abstract

Many applications, such as integrated circuit based digital signal processors (DSPs) and arithmetic logical units (ALUs), rely on adders and subtractors, which are fundamental blocks. Traditional adders and subtractors were created using complementary metal oxide semi-conductor (CMOS) and field effect transistor (FET) technologies, which have increased the number of transistors, path delays, and power consumption. Therefore, this article focuses on the implementation of hybrid adders and subtractors utilizing FinFET and graphene nano-ribbon FET (GnrFET) based nanotechnologies. Initially, a multiplexer logic-based carry output predictable full adder (COPFA) is developed with a fast selection of carry-outputs, which significantly reduces the delays generated in sum estimation. Then, a path selectable reconfigurable hybrid adder (PSRHA) is developed by selecting the high-speed and low-speed carry propagation paths through the COPFA module. Further, a path selectable reconfigurable hybrid subtractor (PSRHS) also developed using two-complement PSRHA addition. Finally, a single architecture for both addition and subtraction are achieved through a joint reconfigurable hybrid adder and subtractor (JRHAS). From the simulations, the COPFA module resulted in a propagation delay (PD) of 7.2792 ns, static power consumption (SPC) of 2.4369nw, and total energy consumption (TEC) of 0.9077 nJ, while the PSRHA module resulted in PD of 2.45317 ns, SPC of 2.55681nw, TEC of 0.0912 nJ. In addition, the PSRHS module resulted in PD as 2.5297 ns, SPC as 2.8428nw, TEC as 0.0662 nJ, and the JRHAS module resulted in PD as 17.178 ns, SPC as 5.4036nw, TEC as 2.0543 nJ. Overall simulations revealed that the proposed COPFA, PSRHA, PSRHS, and JRHAS resulted in optimal performance as compared to conventional methods in terms of power, delay, and energy metrics.