Variety Of Circuits Research Articles

Two-channel opto-electronic chaotic communication system

We propose and implement experimentally an opto-electronic chaotic communication system based on chaos synchronization, which uses two channels: the electronic channel for synchronization and the optical channel for information transmission. Both the transmitter and the receiver contain identical chaotic Rössler-like electronic circuits and identical continuous wave semiconductor lasers. The circuit in the receiver is synchronized with the circuit in the transmitter by one of the variables via the electronic channel, while another variable serves to drive the laser pump current chaotically. Due to the functional dependence of the circuit variables, the signals transmitted through the electronic and optical channels are also functionally dependent. A message is encrypted into the laser output in the transmitter and sent to the receiver via the optical channel, where the received waveform is compared with the laser output in the receiver. Since the lasers in the transmitter and in the receiver are completely synchronized, the message is retrieved with a very good precision.

Row-based FBB: A design-time optimization for post-silicon tunable circuits

Circuit variability has adverse consequences on design predictability and yield in Nanometer CMOS. Post-fabrication tuning approaches have been targeted in a number of recent works to mitigate this problem. Adaptive Body Bias (ABB) is one of the most successful tuning knobs in use today in high-performance custom design. Through forward body bias (FBB), the threshold voltage of the CMOS devices can be reduced after fabrication to bring the slow dies back within the range of acceptable specs. FBB is usually applied with a very coarse granularity at the price of a significantly increased leakage power. We propose a novel, fine-grained FBB scheme on row-based standard cell layout that enables selective forward body biasing of those rows that contain most timing critical gates, thereby reducing leakage power overhead. This style is fully compatible with state-of-the-art commercial physical design flows and imposes minimal area blow-up. It can be applied without any placement disruption on a fully placed design. Benchmark results show large leakage power savings with a maximum savings of 61% in case of 18% compensation in 45nm and 93% in case of 10% compensation in 32nm with respect to block-level approaches.

Improvements in Efficiency of Surface Potential Computation for Independent DG MOSFET

A robust numerical solution of the input voltage equations (IVEs) for the independent-double-gate metal-oxide-semiconductor field-effect transistor requires root bracketing methods (RBMs) instead of the commonly used Newton-Raphson (NR) technique due to the presence of nonremovable discontinuity and singularity. In this brief, we do an exhaustive study of the different RBMs available in the literature and propose a single derivative-free RBM that could be applied to both trigonometric and hyperbolic IVEs and offers faster convergence than the earlier proposed hybrid NR-Ridders algorithm. We also propose some adjustments to the solution space for the trigonometric IVE that leads to a further reduction of the computation time. The improvement of computational efficiency is demonstrated to be about 60% for trigonometric IVE and about 15% for hyperbolic IVE, by implementing the proposed algorithm in a commercial circuit simulator through the Verilog-A interface and simulating a variety of circuit blocks such as ring oscillator, ripple adder, and twisted ring counter.

Performance and Variability Trade-off With Gate-to-Source/Drain Overlap Length

The impact of gate-to-source/drain overlap length on performance and variability of 65 nm CMOS is presented. The device and circuit variability is investigated as a function of three significant process parameters, namely gate length, gate oxide thickness, and halo dose. The comparison is made with three different values of gate-to-source/drain overlap length namely 5 nm, 0 nm, and −5 nm and at two different leakage currents of 10 nA and 100 nA. The Worst-Case-Analysis approach is used to study the inverter delay fluctuations at the process corners. The drive current of the device for device robustness and stage delay of an inverter for circuit robustness are taken as performance metrics. The design trade-off between performance and variability is demonstrated both at the device level and circuit level. It is shown that larger overlap length leads to better performance, while smaller overlap length results in better variability. Performance trades with variability as overlap length is varied. An optimal value of overlap length of 0 nm is recommended at 65 nm gate length, for a reasonable combination of performance and variability.

Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example

This paper presents a design methodology for power and area minimization of flexible FFT processors. The methodology is based on the power-area tradeoff space obtained by adjusting algorithm, architecture, and circuit variables. Radix factorization is the main technique for achieving high energy efficiency with flexibility, followed by architecture parallelism and delay line circuits. The flexibility is provided by reconfigurable processing units that support radix-2/4/8/16 factorizations. As a proof of concept, a 128- to 2048-point FFT processor for 3GPP-LTE standard has been implemented in a 65-nm CMOS process. The processor designed for minimum power-area product is integrated in 1.25 × 1.1 mm2 and dissipates 4.05 mW at 0.45 V for the 20 MHz LTE bandwidth. The energy dissipation ranging from 2.5 to 103.7 nJ/FFT for 128 to 2048 points makes it the lowest energy flexible FFT.

Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits

We present an adaptive technique for compensating manufacturing and environmental variability in subthreshold circuits using “canary flip-flop (FF),” which can predict timing errors. A 32-bit Kogge-Stone adder whose performance was controlled by body-biasing was fabricated in a 65-nm CMOS process. Measurement results show that the adaptive control can compensate process, supply voltage, and temperature variations and improve the energy efficiency of subthreshold circuits by up to 46% compared to worst-case design and operation with guardbanding. We also discuss how to determine design parameters, such as the inserted location and the buffer delay of the canary FF, supposing two approaches: configuration in the design phase and post-silicon tuning.

New technique for inductive power transfer using a single controller

Inductive power transfer (IPT) technology has become a preferred technique for supplying `contactless` power to numerous applications, ranging from microwatt bio-engineering devices to high-power battery charging systems. Typical IPT systems employ two separate controllers, one on the powering or primary side and the other on the receiving or pick-up side of the system, to facilitate contactless power transfer across an air-gap in an efficient and controllable way. This study presents a new IPT control technique, which requires only a single controller, located on the primary side, to effectively regulate the output voltage, which in turn controls the amount of `contactless` power delivery to the pick-up side. The proposed technique uses only the variation in phasor relationship of circuit variables on the primary side to accurately regulate the output voltage or power without any wired or wireless feedback from the secondary side. Theoretical analysis and simulated results are presented, with experimental measurements of a prototype IPT system, to validate the viability of the proposed technique for IPT systems with constant magnetic coupling and single pick-ups. In contrast to existing IPT systems, the proposed IPT system with only a single controller is low in cost, more efficient, and thus can be considered as an attractive choice for many applications.

Comparison of modeling techniques in circuit variability analysis

SUMMARYThree nonlinear reduced‐order modeling approaches are compared in a case study of circuit variability analysis for deep submicron complementary metal‐oxide‐semiconductor technologies where variability of the electrical characteristics of a transistor can be significantly detrimental to circuit performance. The drain currents of 65 nm N‐type metal‐oxide‐semiconductor and P‐type metal‐oxide‐semiconductor transistors are modeled in terms of a few process parameters, terminal voltages, and temperature using Kriging‐based surrogate models, neural network‐based models, and support vector machine‐based models. The models are analyzed with respect to their accuracy, establishment time, size, and evaluation time. It is shown that Kriging‐based surrogate models and neural network‐based models can be generated with sufficient accuracy that they can be used in circuit variability analysis. Numerical experiments demonstrate that for smaller circuits, Kriging‐based surrogate modeling yields results faster than the neural network‐based models for the same accuracy whereas for larger circuits, neural network‐based models are preferred as, in all metrics, better performance is obtained. Within‐die variations for an XOR circuit are analyzed, and it is shown that the nonlinear reduced‐order models developed can more effectively capture the within‐die variations than the traditional process corner analysis. Copyright © 2011 John Wiley & Sons, Ltd.

A Compact Dual-Band 90° Coupler With Coupled-Line Sections

A new dual-band 90° coupler using coupled transmission lines is proposed in this paper. As the coupler consists of only three quarter-wave coupled-line sections, it occupies less circuit area as compared to other existing dual-band branch-line couplers. A desired dual-band operation can be achieved by proper design of the coupling level for those coupled-line sections. Moreover, the coupler's configuration contains a degree of freedom so that its design is “customizable,” allowing itself to be conveniently realized on a variety of circuit and substrate technologies. As a result, it is suitable for use in many practical applications.

Variability, compensation, and modulation in neurons and circuits

I summarize recent computational and experimental work that addresses the inherent variability in the synaptic and intrinsic conductances in normal healthy brains and shows that multiple solutions (sets of parameters) can produce similar circuit performance. I then discuss a number of issues raised by this observation, such as which parameter variations arise from compensatory mechanisms and which reflect insensitivity to those particular parameters. I ask whether networks with different sets of underlying parameters can nonetheless respond reliably to neuromodulation and other global perturbations. At the computational level, I describe a paradigm shift in which it is becoming increasingly common to develop families of models that reflect the variance in the biological data that the models are intended to illuminate rather than single, highly tuned models. On the experimental side, I discuss the inherent limitations of overreliance on mean data and suggest that it is important to look for compensations and correlations among as many system parameters as possible, and between each system parameter and circuit performance. This second paradigm shift will require moving away from measurements of each system component in isolation but should reveal important previously undescribed principles in the organization of complex systems such as brains.

OBSERVATION OF CHAOTIC BEATS IN A DRIVEN MEMRISTIVE CHUA'S CIRCUIT

In this paper, a time varying resistive circuit realizing the action of an active three segment piecewise linear flux controlled memristor is proposed. Using this as the nonlinearity, a driven Chua's circuit is implemented. The phenomenon of chaotic beats in this circuit is observed for a suitable choice of parameters. The memristor acts as a chaotically time varying resistor (CTVR), switching between a less conductive OFF state and a more conductive ON state. This chaotic switching is governed by the dynamics of the driven Chua's circuit of which the memristor is an integral part. The occurrence of beats is essentially due to the interaction of the memristor aided self-oscillations of the circuit and the external driving sinusoidal forcing. Upon slight tuning/detuning of the frequencies of the memristor switching and that of the external force, constructive and destructive interferences occur leading to revivals and collapses in amplitudes of the circuit variables, which we refer as chaotic beats. Numerical simulations and Multisim modeling as well as statistical analyses have been carried out to observe as well as to understand and verify the mechanism leading to chaotic beats.

Seeing Jay-Z in Taipei

How does the newly arrived immigrant respond to the news that an identity already awaits him? How does an African American hip-hop artist translate his struggles and triumphs across oceanic divides? What significance do American demographic shifts have in a global context? Hsu's essay examines what happens once individuals or identities migrate beyond the contexts that first produced them. He explores a variety of circuits: the satellite communities of Asian immigrant students who arrived on American university campuses in the late 1960s; enduring debates about a "post-city" identity, spurred by advances in cheap, efficient, world-shrinking communication technologies; and the new affinities and categories of self-identification made possible by a present-day culture that prizes interactivity and participation.

Computation of the phase and amplitude noise in microwave oscillators and a simplified calculation method for far enough from the carrier offsets

New results regarding phase and amplitude noise analysis in microwave oscillators for moderate offset frequencies from the carrier are presented. Although the phase noise process in an oscillator is a large signal non-stationary process, it is proved that for the purpose of phase noise calculations for moderate offset frequencies, the phase noise process can be considered as a small signal stationary process and by this assumption, a valid approximation of the phase noise spectrum at these offset frequencies is obtained. By this consideration, a simplified approach for the purpose of the phase and amplitude noise spectrum calculations, at far enough from the carrier offset frequencies, by avoiding the numerical ill-conditioning of the harmonic balance equations, is presented. Owing to the presence of the common phase process in the circuit variables, for the practical resolution of the noise relations, it is necessary to introduce an extra constraint on the phase or the amplitude process. Here, it is theoretically proved that this constraint will not change the total noise spectrum of the oscillator. Another form of conversion matrix analysis is presented and the cause of error in the computation of the phase noise at offset frequencies near to the carrier is investigated. The theoretically verified characteristics of phase and amplitude noise analysis methods have been observed in a P-HEMT oscillator at 10.23 GHz.

Memristance in human skin

The memristor is basically a resistor with memory, so that the resistance is dependent on the net amount of charge having passed through the device. It is the regarded the fourth fundamental component, in addition to the resistor, capacitor and inductor, that can be deduced from the four basic circuit variables; current, voltage, charge and magnetic flux. We show that memristors can be used for modelling electrical properties of human skin. In particular is electro-osmosis in human sweat ducts of memristive nature.

Beyond optimality to understanding individual brains: variability, homeostasis and compensation in neuronal circuits

Event Abstract Back to Event Beyond optimality to understanding individual brains: variability, homeostasis and compensation in neuronal circuits Eve Marder1* 1 Brandeis University, United States I will summarize recent theoretical and experimental work that shows that similar circuit outputs can be produced with highly variable circuit parameters. This work argues that the nervous system of each healthy individual has found a set of different solutions that give "good enough circuit performance. I will use examples from theoretical and experimental studies using the crustacean stomatogastric nervous system to argue that synaptic and intrinsic currents can vary far more than the output of the circuit in which they are found. These data have significant implications for the mechanisms that maintain stable function over the animal’s lifetime, and for the kinds of changes that allow the nervous system to recover function after injury. In this kind of complex system, merely collecting mean data from many individuals can lead to significant errors, and it becomes important to measure as many individual network parameters in each individual as possible. Conference: Computational and Systems Neuroscience 2010, Salt Lake City, UT, United States, 25 Feb - 2 Mar, 2010. Presentation Type: Oral Presentation Topic: Oral presentations Citation: Marder E (2010). Beyond optimality to understanding individual brains: variability, homeostasis and compensation in neuronal circuits. Front. Neurosci. Conference Abstract: Computational and Systems Neuroscience 2010. doi: 10.3389/conf.fnins.2010.03.00008 Copyright: The abstracts in this collection have not been subject to any Frontiers peer review or checks, and are not endorsed by Frontiers. They are made available through the Frontiers publishing platform as a service to conference organizers and presenters. The copyright in the individual abstracts is owned by the author of each abstract or his/her employer unless otherwise stated. Each abstract, as well as the collection of abstracts, are published under a Creative Commons CC-BY 4.0 (attribution) licence (https://creativecommons.org/licenses/by/4.0/) and may thus be reproduced, translated, adapted and be the subject of derivative works provided the authors and Frontiers are attributed. For Frontiers’ terms and conditions please see https://www.frontiersin.org/legal/terms-and-conditions. Received: 17 Feb 2010; Published Online: 17 Feb 2010. * Correspondence: Eve Marder, Brandeis University, Waltham, United States, marder@brandeis.edu Login Required This action requires you to be registered with Frontiers and logged in. To register or login click here. Abstract Info Abstract The Authors in Frontiers Eve Marder Google Eve Marder Google Scholar Eve Marder PubMed Eve Marder Related Article in Frontiers Google Scholar PubMed Abstract Close Back to top Javascript is disabled. Please enable Javascript in your browser settings in order to see all the content on this page.

Analysis of Class-E Based RF Power Amplifiers Using Harmonic Modeling

An analysis of the Class-E power amplifier is given using harmonic modeling that facilitates its characterization for a wide load-space regime expected in applications such as RF plasma generation for semiconductor manufacturing. Using a hybrid matrix-framework made up of the dominant harmonics of the circuit variables aided by the time-domain boundary conditions of the power switch voltage waveform, a quasi-linear algorithm is developed to accurately determine the voltage and the current levels expected on all components of the power amplifier for arbitrary loading and operating conditions. The application of the algorithm for design optimization is discussed, and its extension to phase-controlled Class-E power amplifier pairs is described.

A Uniform Nonlinear Control Method for DC-DC Converters with Fast Transient Response

Much effort has been made to the switching surface control of buck converter. However, it remains a fundamental challenge to apply the same concepts and associated control techniques to converters with non-minimum-phase characteristics. A nonlinear control method for all basic DC-DC converters (ie buck converter, boost converter, buck-boost converter, C’ uk converter and SEPIC) is proposed by deriving a uniform switching surface. It retains the advantages of boundary control for buck converter with second-order switching surface. For example, the converters can reach steady state in two switching actions after being subjected to large-signal disturbances. The derivations are general-oriented and can determine the circuit variables needed in the switching function. The same controller is universally applicable to different converters operating in both continuous conduction and discontinuous conduction modes. The potential applications lie in power conversions which require fast response to line/load change...

Stator resistance estimation using ANN in DTC IM drives

Torque control of induction motors (IM) requires accurate estimation of the flux in the motor. But the flux estimate, when estimated from the stator circuit variables, is highly dependent on the stator resistance of the IM. As a result, the flux estimate is prone to errors due to variation in the stator resistance, especially at low stator frequencies. In this paper, an Artificial Neural Network (ANN) is used to adjust the stator resistance of an IM. A back propagation training algorithm was used in training the neural network for the simulation. The proposed ANN resistance estimator has shown good performance in both the transient and steady states. The system is first simulated with computer software and tested by hardware in the loop. Then, it is implemented using a TMS320C6711, 32-bit fixed point Digital Signal Processor (DSP). Experimental and simulated results prove the usefulness and feasibility of the proposed strategy as compared with conventional methods.

Modeling and Simulation of a Transcutaneous Energy Transmission System Used in Artificial Organ Implants

We present a mathematical model to simulate transcutaneous energy transmission systems. Treating such systems as resonant power electronic converters, we develop the equivalent circuit equations, for which the circuit variables are then expanded as Fourier series and a multi-frequency averaging method was applied. Keeping terms up to first-order, the analysis produces a dynamic and harmonic model describing these energy transmission systems. With appropriate values for the circuit parameters, numerical results are compared with those of the exact time domain model. This comparison verifies that our model can adequately represent to first-order such energy-transmission systems.

What is memristor?

The well-known three basic passive circuit elements - resistor (R), capacitor (C), and inductor (L), defines the three mathematical relations connecting the pairings of four fundamental circuit variables: electric current (i), voltage (v), electrical charge (q) and magnetic flux (phi) as: dV = R * di (resistance) dq = C * dv (capacitance) d(phi) = L * di (inductance)