Row-based FBB: A design-time optimization for post-silicon tunable circuits

Abstract

Circuit variability has adverse consequences on design predictability and yield in Nanometer CMOS. Post-fabrication tuning approaches have been targeted in a number of recent works to mitigate this problem. Adaptive Body Bias (ABB) is one of the most successful tuning knobs in use today in high-performance custom design. Through forward body bias (FBB), the threshold voltage of the CMOS devices can be reduced after fabrication to bring the slow dies back within the range of acceptable specs. FBB is usually applied with a very coarse granularity at the price of a significantly increased leakage power. We propose a novel, fine-grained FBB scheme on row-based standard cell layout that enables selective forward body biasing of those rows that contain most timing critical gates, thereby reducing leakage power overhead. This style is fully compatible with state-of-the-art commercial physical design flows and imposes minimal area blow-up. It can be applied without any placement disruption on a fully placed design. Benchmark results show large leakage power savings with a maximum savings of 61% in case of 18% compensation in 45nm and 93% in case of 10% compensation in 32nm with respect to block-level approaches.