Abstract
This work describes how Adaptive Body Biasing can be applied on the Clock Distribution Networks (CDNs) to dynamically compensate the thermally induced skews. By selectively changing the bulk polarizations of the clock buffers, i.e., Forward Body Bias (FBB) to speed-up, or Reverse Body Bias (RBB) to slow down, it is possible to recover the timing phase shifts that accumulate along the clock tree paths due to on-chip thermal gradients.The design constraints that are imposed by the semi-custom layout rules make the physical implementation of the proposed technique a non-trivial task. In fact, such rules require that the biasing should be applied with a relatively coarse granularity, e.g., a row of the layout rather than a single cell.In this paper we propose a row-based Integer Linear Programming (ILP) formulation for identifying a physically constrained optimal body-biasing assignment for thermal clock skew compensation. We also describe a faster linear heuristic that accounts the timing penalties imposed on the logic circuits by the application of the row-based body-biasing.In order to assess the applicability and the effectiveness of the proposed strategies, we benchmarked both the ILP and the heuristic against a cell-based approach using as test cases a set of circuits mapped onto an industrial 40nm technology provided by STMicroelectronics. Experimental results show how a sensible reduction of the thermally induced skew can be achieved, while maintaining compliance with the imposed physical design rules and while keeping timing penalties under control.
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