Chiplet Integration Research Articles

Advanced Mechanical Analysis Workflow for Chiplets Integration Predictive Design

Chiplet-based designs offer a compelling value proposition compared to traditional monolithic System on Chip (SoC) architectures with advantages in IP reuse, performance, cost, and time to market. Mechanical modeling and analysis (M&A) play a critical role in enabling the integration of chiplets, spanning the chip-package-board-system domains to support product development. The integration of chiplets from various suppliers and deverse technologies introduces differences in material properties, thermal coefficients, and mechanical behaviors that presents a significant challenge in ensuring a good mechanical reliability across the chiplet-based integration system. Consequently, chiplet-based designs encounter more challenges to address the elevated mechanical stress and reliability concerns. Traditional mechanical analysis and simulation workflows are primarily tailored for monolithic SoC-based designs and are not readily applicable to chiplet-based designs. The latter can no longer afford to overlook issues related to mechanical and thermal stress induced by multiple chiplets, especially with the use of advanced 2.5D and high-density fanout packages. In this paper, an advanced mechanical analysis workflow for chiplet-based designs is proposed. The representative examples that demonstrate the efficacy of this workflow are also presented. The advanced mechanical analysis workflow involves modeling of chiplets interactions at the early design stage spanning from the Si level to package level and encompassing scales from micrometers to millimeters that includes the components such as Through-Silicon Vias (TSVs), HIgh Density Fanout Cu RDL (Redistribution Layer) and microbumps. Furthermore, the predictive mechanical analysis workflow extends to analyses at the millimeter to meter scale, considering entire systems and incorporating elements like heat sinks and printed circuit boards (PCBs). It represents a multifaceted process spanning chip-to-package co-design, stress analysis, thermal analysis, failure analysis, and chiplet-based design optimization.

Materials-Technology Co-Optimization (MTCO) for Inter-Die-Gap-Fill (IDGF) in Heterogeneous Integration of Chiplets

Materials-Technology Co-Optimization (MTCO) is used to engineer Plasma-Enhanced Chemical Vapor Deposition (PECVD) of dielectric material properties for the Inter-Die-Gap-Fill (IDGF) between bonded chiplets in 2D and 3D heterogeneous integration. Mechanical properties of the dielectric IDGF are accurately tuned to eliminate cracking due to external forces in the next planarization processes. Thermal properties of the dielectric IDGF are tuned to effectively reduce thermal stress and eliminate cracking through downstream anneal and deposition processes. We demonstrate a working process flow to evaluate mechanical and thermal cracking stability of the IDGF material for heterogenous integration development.

Multiphysics Simulation of Chiplet Integration Process-Induced Stress Effects on AC and DC Quantum Transport of FinFET From System Technology Co-Optimization Perspective

Multiphysics Simulation of Chiplet Integration Process-Induced Stress Effects on AC and DC Quantum Transport of FinFET From System Technology Co-Optimization Perspective

Fabrication and Formation Principle of Porous Cu–Sn Bumps for Metal Bonding in Chiplet Integration

Fabrication and Formation Principle of Porous Cu–Sn Bumps for Metal Bonding in Chiplet Integration

Study on no IMC Solid state bonding method for high-density 2.5D/3D integration

Abstract Chiplet integration is a new development direction for the continuation and even goes beyond Moore’s Law, and in order to achieve the high density, high reliability, high-speed Chiplet device, a new method of 2.5D/3D integration approach is needed to fulfill the needs to Chiplet heterogeneous devices. In this work, two dies were successfully bonded via low energy input with no IMC solid state bonding under 220°C and 5 MPa, which is much gentler than the other solid state bonding approaches. Each die had a matrix of 22500 Cu pillars with a diameter of 20 μm. This method was promising for the near future high-density 2.5D/3D integration.

In-process Warpage Prediction and Optimization for Heterogeneously Integrated Packages Using a Novel Thermo-mechanical Modeling Scheme

Modern-day semiconductor packages have been focusing on heterogeneous integration of chiplets to enable multiple functionalities, improve device performance and reduce manufacturing cost. A class of heterogeneous integration schemes involves reconstitution of known good dies using epoxy mold compound (EMC) and formation of redistribution layers (RDLs) to fanout electrical connections from the chips to a larger pitch compatible with that of the substrate pads. Typically, this reconstitution and RDL processing are performed at wafer-level. Subsequently, the reconstituted wafer is diced to singulate the molded chip-modules which are then assembled onto the substrates. Depending upon the physical properties of different materials involved in the fabrication process, their relative proportions and processing temperatures, the wafer-level warpage during the process can become very high and fluctuate between the convex and concave shapes. This could make the fabrication process and wafer handling very challenging. Hence, it is important to control the in-process wafer warpage. Here, we develop a novel thermo-mechanical modeling scheme utilizing the finite element method that can predict (i) the evolution of the wafer-level warpage during the fabrication process, (ii) warpage of the singulated chip-module, and (iii) warpage evolution during the package assembly process. The model incorporates effects of large deformation, material addition or removal during the fabrication process, and chemical shrinkage of polymer materials. For a typical multi-die molded packaging process, we analyze using this model, effects of (i) mold to silicon area ratio, (ii) number of dies and spacing between them, (iii) number of RDLs, (iv) properties of temporary carrier, and (v) properties of EMC material on wafer-level in-process warpage and package warpage. Subsequently, we propose optimal values of material and process parameters that reduce the warpage. The modeling approach presented in this work will help optimize package fabrication and assembly processes without having to build multiple legs of a test vehicle.

Adaptive Patterning Techniques for the Chiplet Era

As the industry has evolved to deliver heterogenous integration, chiplets, and high-density interconnect, so has Deca’s Adaptive Patterning (TM) (AP) technology. Wafer and panel fan-out, fan-out on substrate, and other embedded die interconnect technologies all have inherent natural variations in the manufacturing process, with die-shift typically having the highest impact. Rather than fight variation by using high accuracy, lower throughput equipment, AP takes a different approach and accommodates variation through real-time design-during-manufacturing. First a high-speed optical scanner measures the actual position of each die, next the AP software system generates a unique per-unit lithography pattern adapted to its individual measurement, and finally the specific per-unit patterns are implemented with a single-pass, mask-less lithography system. Techniques such as Adaptive Alignment for single-die, and Adaptive Routing for multi-die integration are used to enable the highest density design rules. This publication will present two newly developed AP techniques that allow further scaling to high density interconnect. The first, Progressive Adaptive Alignment, extends previous techniques to allow distribution of the die-shift across all layers in the stack-up. Example design studies will be shown to illustrate the advantages for fan-out on substrate and package-on-package (PoP). The second technique, Adaptive Shapes, dynamically redesigns power planes, signal planes, and fill metal to account for measured die-shift. Adaptive power planes and signal planes provide robust signal integrity for multi-die integration, while dynamic metal fill optimizes the topography in multi-RDL products, delivering real-time design-for-manufacturing (DFM). An example design study with multiple HBM memory interfaces will explore possible applications and benefits for designs with 2µm, and finer, lines. These Adaptive Patterning techniques offer a compelling solution for chiplet integration. Removing traditional fixed photomasks from the equation breaks through conventional barriers to fine-pitch, high density, and high-yield for embedded die structures.

Using Deca’s Adaptive PatterningTM to Win the Chiplet Integration Race with Siemens EDA and ASE

As the need for chiplet integration becomes more prevalent in industry, the current standard of silicon interposers is not sustainable for broad adoption. Among the top technologies competing in this race are embedded bridge chip structures, chips-last fan-out, and chips first-fan out. Deca’s M-SeriesTM, a fully organic chips-first planar structure, promises a new way to achieve equivalent density to benchmark high density interconnects without the need for the complex structures and processes. Deca Technologies, Siemens EDA, and ASE formed a collaboration to design, verify, build, and perform physical analysis on an M-Series chiplet test vehicle. For this proof of concept, a 10-die chiplet package was designed using Siemens EDA’s Xpedition high density advanced packaging (HDAP) technologies. Siemens EDA’s Calibre was then used to perform verification and signoff. With design, verification and signoff complete, follow up plans are to build a test vehicle with ASE for physical characterization. Deca’s technology has surpassed other fan-out technologies in the chiplet integration race with Adaptive Patterning achieving significantly higher density for both vias and traces while enabling designs with the tightest device bond pad pitch. The planar surface of M-Series enables trace width and spacing of 2 microns and Adaptive Patterning makes possible a smaller copper stud size (competitors add an additional copper layer to increase the size) yielding a 20 micron copper stud pitch. In addition to an 80% reduction in the area required for a set number of copper studs, this technology also provides the highest integrity electrical connections with superior via contact areas. When compared to competing technologies, a 500% increase in via contact area can be achieved for the same bond pad pitch. This test vehicle design proves that Adaptive Patterning provides a compelling solution which surpasses competitors in the chiplet integration race.

Hybrid Bonding for Ultra-High-Density Interconnect

Abstract Hybrid bonding is the technology for interchip ultrahigh-density interconnect at pitch smaller than 10 μm. The feasibility at wafer-to-wafer level bonding with bond pad pitch of sub-0.5 μm has been demonstrated with scaling limitations under exploration beyond sub-0.4 μm. The heterogeneous integration of chiplets often requires die-to-wafer hybrid bonding for diverse chip stacking architectures. This overview emphasis on some main issues associated with hybrid bonding extending to die-to-wafer level. The hybrid bond pad structure design is a critical factor affecting sensitivity to overlay accuracy, copper recess or protrusion requirements, and performances. Cases of hybrid bonding schemes and pad structure designs are summarized and analyzed. Performance assessment and characterization methods are briefly overviewed. The scalability of pad pitch is addressed by analyzing the recent literature reports. Challenges of managing singulated dies for die-to-wafer bonding with direct placement or collective die-to-wafer bonding schemes under exploration are addressed. Nonetheless, industry collaboration for manufacturing equipment development and industry standards on handling chiplets from different technology nodes and different factories are highlighted.

High-performance, power-efficient three-dimensional system-in-package designs with universal chiplet interconnect express

Universal chiplet interconnect express (UCIe) is an open industry standard interconnect for a chiplet ecosystem in which chiplets from multiple suppliers can be packaged together. The UCIe 1.0 specification defines interoperability using standard and advanced packaging technologies with planar interconnects. Here we examine the development of UCIe as the bump interconnect pitches reduce with advances in packaging technologies for three-dimensional integration of chiplets. We report a die-to-die solution for the continuum of package bump pitches down to 1 µm, providing circuit architecture details and performance results. Our analysis suggests that—contrary to trends seen in traditional signalling interfaces—the most power-efficient performance for these architectures can be achieved by reducing the frequency as the bump pitch goes down. Our architectural approach provides power, performance and reliability characteristics approaching or exceeding that of a monolithic system-on-chip design as the bump pitch approaches 1 µm.

LBDR: A load-balanced deadlock-free routing strategy for chiplet systems

Chiplet integration technology offers enhanced performance and reduced costs by breaking down a large chip into smaller chiplets, which are then interconnected using advanced packaging technology. However, the current chiplet interconnects give priority to correctness concerns rather than load balancing issues. While prioritizing correctness aims to prevent deadlocks, a system that is free of deadlocks can still experience load imbalances that compromise its overall performance. This paper presents the LBDR strategy, which is a load-balanced deadlock-free routing strategy for chiplet systems, and effectively enhances the system performance. Firstly, we develop a novel boundary nodes selection criterion and a heuristic algorithm based node binding mechanism to maintain a balanced load on vertical links for each chiplet’s outbound traffic. Secondly, we select turn restrictions at the boundary nodes to ensure that inbound traffic flows evenly into the chiplet, while maintaining a deadlock-free system. Experiments using the Garnet in gem5 simulator show that this strategy outperforms existing methods in terms of load balancing, throughput, and latency, and is applicable to a variety of traffic scenarios.

From 2D to 3D, “Chiplet Integration” Enabling the “More Moore” Trend

From 2D to 3D, “Chiplet Integration” Enabling the “More Moore” Trend

Interconnect Design for Heterogeneous Integration of Chiplets in the AMD Instinct™ MI300X Accelerator

Interconnect Design for Heterogeneous Integration of Chiplets in the AMD Instinct™ MI300X Accelerator

PDN analysis of 3D chiplet integration with a DC-DC converter on active interposer

PDN analysis of 3D chiplet integration with a DC-DC converter on active interposer

Heterogeneous Integration of Chiplets, Lego-like IP for More than Moore

The semiconductor industry is facing an inflection point as higher cost, lower yield, and reticle size limitations drive the need for viable alternatives to traditional monolithic solutions, which are hitting or coming close to the limits of manufacturing and physics. This is driving an emerging trend to disaggregate what typically would be implemented as an SoC into solid, fabricated IP blocks, otherwise known as chiplets. These chiplets typically provide a specific function implemented in an optimal chip process node. Several chiplets and an optional, custom SOC device mounted and interconnected in a single packing using high speed/bandwidth interfaces that will then deliver monolithic or greater performance at a reduced cost, higher yield, and with only a slightly larger area as a heterogeneous integrated advanced package. As fabless semiconductor companies begin to bring these disaggregated chiplets to market, their successful adoption requires the fabless semiconductor industry to standardize on a set of interface protocols that will offer Lego-like plug and play compatibility between different suppliers chiplets creating a truly open ecosystem and supply chain. When it comes to the physical heterogeneous integration of these chiplets it is typically achieved using a high-performance silicon-like interposer substrate. Such substrates typically require silicon-like design rules and design techniques along with their own specific analysis and verification requirements. The supply chain for these substrates does not change significantly, it is still typically the leading semiconductor foundries and OSATs however the level of interaction, requirements, and signoff approvals does change bringing often new demands and challenges. Is this a revolution or an evolution, it depends on your starting point? Does it need an entirely new set of workflows and design tools? Can we evolve in some stepwise linear process from where we are today with monolithic or traditional system-in-package type designs into this next-generation design environment? This paper will explore these new challenges and outline 5 key workflows that address and manage them. These 5 workflows span interlinked domain areas starting with architecture definition before progressing to design that incorporates planning, prototyping, and technology co-optimization of the chosen architecture as well as the detailed physical implementation of substrates before moving to multi-physics analysis, device-level test, and then manufacturing. This paper will then recommend workflow adoption focus areas that we have seen provide immediate heterogeneous integration capability benefits while providing a managed methodology adoption and migration process that minimizes disruption, risk, and of course cost that can bring heterogeneous integration based chiplet design within reach of the mainstream instead of only being accessible to the mega iDMs and fabless semi’s.

D2W Hybrid Bonding Using High Accuracy Carrier Solutions for 3D System Integration

Die segmentation and chiplet integration is gaining considerable industry momentum and seen as one important integration process for 3D systems on chips. As interconnect pitches in 3D packaging become tighter with each new product generation, wafer and die bond alignment and overlay processes must also scale accordingly. 10µm pitch is setting a junction in interconnect technology. On the one hand, it is seen as the inflection point of hybrid bonding. At the same time, these extremely tight pitches enable functional partitioning of device functions onto different dies (chiplets) using die-to-wafer (D2W) hybrid bonding or wafer-to-wafer (W2W) hybrid bonding. D2W hybrid bonding is evaluated in different integration processes. While direct placement of fusion bondable dies from a film frame is researched intensely, another option is to reconstitute dies on a carrier wafer and collectively transfer the dies using W2W bonding equipment. In the presentation we will elaborate on all aspects of the die to wafer bonding for a successful single chip type process towards a full system transfer approach. We will show alignment data of the dies on the transfer carrier targeting a pick and place accuracy of <500nm and report on the alignment evolution during the process until final annealing. Further elaboration will be done on different die sizes and die thicknesses. The die flatness and high variation over the whole wafer will be evaluated according to the die dimensions. Most importantly the die high variation and planarity will be shown for different carrier systems such as thermoset and thermoplastic materials, evaluating the bonding performance in terms of alignment propagation bond line integrity.

Scaling Interconnect Densities Meeting the Growing Demand for Chiplet Integration

With the increasing demand for heterogenous chiplet integration, the demand for high density chip to chip interconnects grows equivalently. In 2022 there were two significant announcements on breakthroughs in chip integration. At the highest end is AMD’s v-cache, which utilizes hybrid bonding to make connections between cache and processor. Also introduced to industry, was Apple’s M1-Ultra processor which achieves advanced flip-chip pitch at 25µm x 35µm. Through teardowns it is apparent that the M1-Ultra is made up of two chips first embedded processors, a flip-chip bridge, and molded fanout technology. These silicon-based solutions are complex and costly, but they demonstrate the industry’s strong demand for high density interconnects. This paper outlines an alternate approach to achieving high density die-to-die interconnects through purely organic wafer or panel level packaging (PLP) that can meet or exceed the density provided by a silicon bridge. Deca Technologies’ Gen 2 M-Series™ fan-out with Adaptive Pattering® provides 20µm pitch capability with 2µm line and space widths. This interconnect density can match or exceed that offered by a silicon bridge, while significantly reducing the cost and yield risk. A specific 10 die test vehicle build will be presented that demonstrates this capability. This 20µm pitch is only the starting point as the technology will continue to scale. Through the new, MDX™ technology, capture pads are eliminated from all metal layers allowing unprecedented routing density increases on organic fan-out structures in combination with finer device interface pitch. While the details of this technology are still proprietary, a high-level overview will be provided.

Challenges in Developing Three-dimensional Chiplet Integration Technologies at the IBM T.J. Watson Research Center

Challenges in Developing Three-dimensional Chiplet Integration Technologies at the IBM T.J. Watson Research Center

TSV Integration With Chip Level TSV-to-Pad Cu/SiO₂ Hybrid Bonding for DRAM Multiple Layer Stacking

55 μm depth TSV-to-pad Cu/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> hybrid bonding for the integration of Si interposer and DRAM has been demonstrated by room temperature bonding and an annealing process. Optimization of surface pretreatment is the key to bonding of Cu and SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> with high quality at the same time. In addition, the TSV protrusion issue, which would cause failure of multiple layer stacking, was effectively improved by Cu grain stabilization process and pre-treatment adjustment. The electrical measurements were performed, showing the low and stable TSV resistance. Thus, the TSV-to-pad hybrid bonding with no μ-bumps is promising for further scaling and stacking in HBM or chiplet integration scenarios.

Chiplet Integration Technology by Suspended Bridge Architecture

Chiplet Integration Technology by Suspended Bridge Architecture