Heterogeneous Integration of Chiplets, Lego-like IP for More than Moore

Abstract

The semiconductor industry is facing an inflection point as higher cost, lower yield, and reticle size limitations drive the need for viable alternatives to traditional monolithic solutions, which are hitting or coming close to the limits of manufacturing and physics. This is driving an emerging trend to disaggregate what typically would be implemented as an SoC into solid, fabricated IP blocks, otherwise known as chiplets. These chiplets typically provide a specific function implemented in an optimal chip process node. Several chiplets and an optional, custom SOC device mounted and interconnected in a single packing using high speed/bandwidth interfaces that will then deliver monolithic or greater performance at a reduced cost, higher yield, and with only a slightly larger area as a heterogeneous integrated advanced package. As fabless semiconductor companies begin to bring these disaggregated chiplets to market, their successful adoption requires the fabless semiconductor industry to standardize on a set of interface protocols that will offer Lego-like plug and play compatibility between different suppliers chiplets creating a truly open ecosystem and supply chain. When it comes to the physical heterogeneous integration of these chiplets it is typically achieved using a high-performance silicon-like interposer substrate. Such substrates typically require silicon-like design rules and design techniques along with their own specific analysis and verification requirements. The supply chain for these substrates does not change significantly, it is still typically the leading semiconductor foundries and OSATs however the level of interaction, requirements, and signoff approvals does change bringing often new demands and challenges. Is this a revolution or an evolution, it depends on your starting point? Does it need an entirely new set of workflows and design tools? Can we evolve in some stepwise linear process from where we are today with monolithic or traditional system-in-package type designs into this next-generation design environment? This paper will explore these new challenges and outline 5 key workflows that address and manage them. These 5 workflows span interlinked domain areas starting with architecture definition before progressing to design that incorporates planning, prototyping, and technology co-optimization of the chosen architecture as well as the detailed physical implementation of substrates before moving to multi-physics analysis, device-level test, and then manufacturing. This paper will then recommend workflow adoption focus areas that we have seen provide immediate heterogeneous integration capability benefits while providing a managed methodology adoption and migration process that minimizes disruption, risk, and of course cost that can bring heterogeneous integration based chiplet design within reach of the mainstream instead of only being accessible to the mega iDMs and fabless semi’s.