LBDR: A load-balanced deadlock-free routing strategy for chiplet systems

Abstract

Chiplet integration technology offers enhanced performance and reduced costs by breaking down a large chip into smaller chiplets, which are then interconnected using advanced packaging technology. However, the current chiplet interconnects give priority to correctness concerns rather than load balancing issues. While prioritizing correctness aims to prevent deadlocks, a system that is free of deadlocks can still experience load imbalances that compromise its overall performance. This paper presents the LBDR strategy, which is a load-balanced deadlock-free routing strategy for chiplet systems, and effectively enhances the system performance. Firstly, we develop a novel boundary nodes selection criterion and a heuristic algorithm based node binding mechanism to maintain a balanced load on vertical links for each chiplet’s outbound traffic. Secondly, we select turn restrictions at the boundary nodes to ensure that inbound traffic flows evenly into the chiplet, while maintaining a deadlock-free system. Experiments using the Garnet in gem5 simulator show that this strategy outperforms existing methods in terms of load balancing, throughput, and latency, and is applicable to a variety of traffic scenarios.