TSV Integration With Chip Level TSV-to-Pad Cu/SiO₂ Hybrid Bonding for DRAM Multiple Layer Stacking

Abstract

55 μm depth TSV-to-pad Cu/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> hybrid bonding for the integration of Si interposer and DRAM has been demonstrated by room temperature bonding and an annealing process. Optimization of surface pretreatment is the key to bonding of Cu and SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> with high quality at the same time. In addition, the TSV protrusion issue, which would cause failure of multiple layer stacking, was effectively improved by Cu grain stabilization process and pre-treatment adjustment. The electrical measurements were performed, showing the low and stable TSV resistance. Thus, the TSV-to-pad hybrid bonding with no μ-bumps is promising for further scaling and stacking in HBM or chiplet integration scenarios.