Abstract

Die segmentation and chiplet integration is gaining considerable industry momentum and seen as one important integration process for 3D systems on chips. As interconnect pitches in 3D packaging become tighter with each new product generation, wafer and die bond alignment and overlay processes must also scale accordingly. 10µm pitch is setting a junction in interconnect technology. On the one hand, it is seen as the inflection point of hybrid bonding. At the same time, these extremely tight pitches enable functional partitioning of device functions onto different dies (chiplets) using die-to-wafer (D2W) hybrid bonding or wafer-to-wafer (W2W) hybrid bonding. D2W hybrid bonding is evaluated in different integration processes. While direct placement of fusion bondable dies from a film frame is researched intensely, another option is to reconstitute dies on a carrier wafer and collectively transfer the dies using W2W bonding equipment. In the presentation we will elaborate on all aspects of the die to wafer bonding for a successful single chip type process towards a full system transfer approach. We will show alignment data of the dies on the transfer carrier targeting a pick and place accuracy of <500nm and report on the alignment evolution during the process until final annealing. Further elaboration will be done on different die sizes and die thicknesses. The die flatness and high variation over the whole wafer will be evaluated according to the die dimensions. Most importantly the die high variation and planarity will be shown for different carrier systems such as thermoset and thermoplastic materials, evaluating the bonding performance in terms of alignment propagation bond line integrity.

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