Scaling Interconnect Densities Meeting the Growing Demand for Chiplet Integration

Abstract

With the increasing demand for heterogenous chiplet integration, the demand for high density chip to chip interconnects grows equivalently. In 2022 there were two significant announcements on breakthroughs in chip integration. At the highest end is AMD’s v-cache, which utilizes hybrid bonding to make connections between cache and processor. Also introduced to industry, was Apple’s M1-Ultra processor which achieves advanced flip-chip pitch at 25µm x 35µm. Through teardowns it is apparent that the M1-Ultra is made up of two chips first embedded processors, a flip-chip bridge, and molded fanout technology. These silicon-based solutions are complex and costly, but they demonstrate the industry’s strong demand for high density interconnects. This paper outlines an alternate approach to achieving high density die-to-die interconnects through purely organic wafer or panel level packaging (PLP) that can meet or exceed the density provided by a silicon bridge. Deca Technologies’ Gen 2 M-Series™ fan-out with Adaptive Pattering® provides 20µm pitch capability with 2µm line and space widths. This interconnect density can match or exceed that offered by a silicon bridge, while significantly reducing the cost and yield risk. A specific 10 die test vehicle build will be presented that demonstrates this capability. This 20µm pitch is only the starting point as the technology will continue to scale. Through the new, MDX™ technology, capture pads are eliminated from all metal layers allowing unprecedented routing density increases on organic fan-out structures in combination with finer device interface pitch. While the details of this technology are still proprietary, a high-level overview will be provided.