Chip Embedding Research Articles

Wafer Level Chip Size Package Integration of an Aero-acoustic MEMS Microphone into a Thin and Flexible Substrate

This publication describes a novel combination of a chip-scale-package-approach for micro-electromechanical systems with flush surface chip embedding in thermal Polyurethane. The concept enables the fabrication of thin and flexible substrates in which sensor chips with fragile membranes are integrated. The presented sensor array can be used for applications like sound source localization in streams of passenger airplanes whilst test-flights.

Low dead space encapsulation and integration of circuits for retinal prosthesis based on cyclic olefin copolymer.

A retinal prosthesis is a device that can provide artificial vision to people who have lost their sight from certain retinal disorder. Because the device needs to be inserted into the body, high flexibility and reliability is required. Recently, devices using thermoplastic polymers such as LCP and COC as substrates have been studied. Being a highly functional integrated device, retinal prosthesis poses many design challenges. Among them, the stimulation chip embedding can be a particularly important task. Although it is common to use a wire bonding method for chip embedding, there are several limitations that are difficult to apply to implantable device. In this investigation, a novel approach is developed for high spaceefficient electrical connections and perform reliable encapsulation of integrated circuits to replace wire bonding. Since designing and manufacturing the stimulator chip used in retinal prosthesis requires non-negligible cost, a silicon die with the identical shape was selected as a substitute for testing purposes.

D-Band Integrated and Miniaturized Quasi-Yagi Antenna Array in Glass Interposer

An integrated and miniaturized D-band quasi Yagi antenna in glass interposer is presented. Single element, 1×2 and 1×4 test coupons are fabricated on 100-μm glass substrate with low-loss polymer buildup films and the return loss, gain and radiation pattern of the antennas are characterized. The proposed antenna utilizes a monopole radiator to achieve a higher bandwidth. Advantages of the glass substrate for beyond 5G communications in terms of enabling fine features and compact integration of other active and passive devices through chip embedding is discussed. An analysis of the substrate modes to ensure proper mode propagation in the selected stack-up is presented. Furthermore, the paper discusses the challenges in planar antenna measurements in sub-THz frequencies and it presents two measurement setups to overcome these challenges. The first is a low-cost probe-station-based measurement setup to characterize the return loss and boresight gain, and the second is a diode-detector-based setup to measure the normalized radiation pattern. The proposed antennas achieve high bandwidth covering the frequency range of 110-170 GHz, and 4.78 dBi, 8.41 dBi, and 11.04 dBi gain for the single element, 1×2 and 1×4 array, respectively.

HGCROC2: the front-end readout ASICs for the CMS High Granularity Calorimeter

The CMS High-Granularity Calorimeter (HGCAL) imposes extremely challenging specifications for the front-end electronics: high dynamic range, low noise, high-precision time information and low power consumption, as well as the need to select and transmit trigger information with a high transverse and longitudinal granularity. HGCROC2 is the second prototype of the readout chip embedding almost all the final functionalities. It has 72 channels of the full analog chain: low noise and high gain preamplifier and shapers, a 10-bit 40 MHz SAR-ADC which provides the charge measurement over the linear range of the preamplifier, after the preamplifier saturation a discriminator and TDC provide the charge information from ToT (200 ns dynamic range and 50 ps binning), and a fast discriminator and TDC provide timing information to 25 ps accuracy. This paper reports on the performance in terms of noise, charge and timing, the DAQ and Trigger paths, as well as results from radiation qualification with total ionizing dose (TID) and heavy ions for single-event effects (SEE).

Embedded-Component Planar Fan-Out Packaging for Biophotonic Applications

Embedded-chip planar silver-elastomer interconnect technology is developed with flexible substrates and demonstrated for on-skin biophotonic sensor applications. This approach has several benefits and is also consistent with chip-thinning where the chip thickness is 100 microns and less. The key benefits from this approach arise because both the bottom and top sides are now available as flat surfaces for 3D integration of other components. It also results in the lowest electrical parasitics compared to flipchip with adhesives or printed-ramp interconnections with surface-assembled devices. Embedding of chips in flexible carriers was accomplished with direct screen-printed interconnects onto the chip pads in substrate cavities. Silver nanoflake-loaded polyurethane is utilized in the embedded-chip packages to provide the desired lower interconnect resistance and also reliability in flexible packages under deformed configurations. Viscoelastic models were utilized to model the interconnection stresses. Planar interconnects in flexible substrates are developed with conductive silver-loaded elastomer interconnects. This approach is compared to direct chip-on-flex assembly technology for reliability under bending and high-temperature storage. The embedded-chip technology is demonstrated through biophotonic sensor applications where light sources (LEDs) and photodetectors are embedded inside the package. Functional validation in bent configuration at low curvatures is shown by measuring pulse rate and muscle activity with human subjects. By extending this technology to nanowires in elastomers, further enhancement in electrical and reliability performance can be achieved.

Embedding of Ultrathin Chips in Highly Flexible, Photosensitive Solder Mask Resist.

This work presents an embedding process for ultrathin silicon chips in mechanically flexible solder mask resist and their electrical contacting by inkjet printing. Photosensitive solder mask resist is applied by conformal spray coating onto epoxy bonded ultrathin chips with a daisy chain layout. The contact pads are opened by photolithography using UV direct light exposure. Circular and rectangular openings of 90 µm and 130 µm diameter, respectively, edge length are realized. Commercial inks containing nanoparticular silver and gold are inkjet printed to form conductive tracks between daisy chain structures. Different numbers of ink layers are applied. The track resistances are characterized by needle probing. Silver ink shows low resistances only for multiple layers and 90 µm openings, while gold ink exhibits low resistances in the single-digit Ω-range for minimum two printed layers.

Characterization of On-Foil Sensors and Ultra-Thin Chips for HySiF Integration

The characterization of multiple mechanically flexible passive and active electronic components, namely on-foil temperature sensor, relative humidity sensor, and ultra-thin microcontroller unit (MCU) integrated circuit (IC) is presented. These components are readily available for Hybrid System-in-Foil (HySiF) integration, which combines the merits of the high-performance silicon chips with the large-area electronics. The 60-nm thin-film resistance temperature detector (RTD) is fabricated on different substrates and the extracted temperature coefficient ranges from 0.002 to 0.003( $\Omega/\Omega$ )/°C. Furthermore, the capacitive relative humidity sensor is fabricated by utilizing a polymeric sensing dielectric material that is compatible with those polyimides used in ultra-thin chip embedding. The $1-\mu \text {m}$ thick sensor achieves a fast adsorption rise time of $\text {54 ms}$ and a spontaneous desorption fall time of $\text {750 ms}$ . For flexible ICs packaging and HySiF integration, microcontroller chips are back-thinned to a thickness of about ${30}~\mu \text {m}$ . The characterization of the MCU after the thinning process step showed undegraded performance of the integrated analog-to-digital converter in terms of linearity. However, a drop in the on-chip temperature sensor sensitivity is observed for the thin chips and significant degradation in the period jitter of the high-frequency RC oscillator is measured. Finally, continuity tests are performed to validate the functionality of the ultra-thin MCUs when embedded using the Chip-Film Patch (CFP) flexible package.

Chip-Package-Board Reliability of System-in-Package Using Laminate Chip Embedding Technology Based on Cu Leadframe

We investigate the reliability of a system-in-package (SiP) technology, which uses laminate chip embedding based on a copper leadframe. For this SiP technology, we apply different Si-based transistor technologies. We test the reliability of three types of chip-embedded packages: a single-chip embedded package (SCP) with an embedded MOSFET test chip for basic understanding, and two SiPs—a multichip embedded package (MCP) with a dc/dc converter for industrial applications and a SiP for lighting applications. In order to better represent specific field stresses for the target applications, we develop and investigate new test methods for laminate-based packages. In this article, we report the design, the implementation, and the results of those new methods and discuss their benefits and validity. We conducted conventional test methods like temperature humidity bias (THB) for comparison. The results of all these tests demonstrate a very good reliability of the chip-embedded packages. We also investigate early damages inside the packages using failure analysis techniques such as cross sectioning. The cooperation of partners along the value chain resulted in a coherent understanding of chip-package-board material aspects and design for reliability.

Design and Demonstration of Glass Panel Embedding for 3D System Packages for Heterogeneous Integration Applications

Abstract This article demonstrates a next-generation high-performance 3D packaging technology with smaller form factor, excellent electrical performance, and reliability for heterogeneous integration. High-density logic-memory integration, today, is built predominantly using interposers which are fundamentally limited in assembly pitch and interconnect lengths, and they also are expensive as the package sizes increase. On the other hand, high-frequency applications continue to use laminates which are also limited by package size and ability to integrate many components. Wafer-level fan-out (WLFO) packaging promises better performance and form factor at lower costs, but current WLFO packages are mold-based and hence are limited to small packages. This article presents a 3D packaging technology using glass panel embedding (GPE) for high-performance with potential for large body size heterogeneous integration applications. The tailorable coefficient of thermal expansion of glass allows a reliable direct board attach of large GPE packages that not only benefits the form factor and signal speed but also provides radical benefits to power delivery. Unlike interposers and silicon bridges, GPE packages are not bump-limited and can support I/O densities comparable with backend-of-line with silicon-like redistribution wiring at much lower costs. The fundamental limitations such as die shift and poor dimensional stability of current organic WLFO packages are addressed by parametric process improvements to reduce die shift to <2 μm while also improving the RDL surface planarity for high-yielding fine-line structures and integrating through glass via (TGV) in the fan-out region for 3D packaging. This article describes the fabrication process for 3D GPE, leading to demonstration of a technology using embedding of chips with all-Cu interconnections at 40-μm I/O pitch with TGVs at 300-μm pitch, thus enabling double-side RDL and assembly of chips to achieve three levels of device integration.

Embedding Mosfets

A new technology that uses chip embedding of power MOSFETs in PCBs can meet increasing requirements for electrical power management systems

Embedded SIP Modules for next-GEN Heterogeneous “POWER-Devices”

In this paper will focus on the comprehension of System-in-Package (SiP) with embedded active and passive components integration will be described. Embedding of semiconductor chips into substrates provides many advantages that have been noted. It allows the smallest package form-factor with high degree of miniaturization through sequentially stacking of multiple layers containing embedded devices that are optimized for electrical performance with short and geometrically well controlled copper interconnects. In addition, the embedding gives a homogeneous mechanical environment of the chips, resulting in good reliability at system level. Furthermore, embedded technology is an excellent resolution to Power management challenges dealing with new device technologies (Si, GaS, GaN) and optimization on the thermal dissipation with improved efficiency. Embedded technology comes with many challenges in 2019, primarily design for manufacturability (DFM) and maturity. Customers are looking for better-performance capability and pricing normally that means same or lower than die free package cost (DFPC) comparison. This paper will discuss the challenges bring to market the Embedded SIP Modules for next-GEN Heterogeneous “POWER-Devices” Today, the embedded process is being developed by printed circuit board (PCB) manufacturers creating a new supply chain, bringing new players into the semiconductor industry. This new supply chain comes along with new business models. As a result of the increasing interest in implementing embedding technologies, ACCESS Semiconductors in China is committed to be a leader in the adaptation of embedding technologies, with over 10-yrs mature coreless technology and proved design rules for low profile dimensions with seamless Ti/Cu sputtering and Cu pillar interconnect giving advantages in both electrical & power performance. ACCESS Patented “Via-in-Frame” technology provides High Reliability (MSL1, PCT, BHAST) at Cost Effective in high panel utilization for HVM, using standard substrate/PCB known material sets, no need for wafer bumping/RDL, over-mold or under-fill cost adders. ACCESS Semiconductors is currently in HVM on single die 2L, and LVM on multi-devices actives/passives 4L SiP construction both platforms are driven from the power market segment. In-development on Die Last & Frameless (MeSiP) platforms utilizing hybrid technology (mSAP) and Photo Imageable Dielectric (PID) materials for cost down solutions in HVM by Q1FY2020. Also, ACCESS Semiconductors total turn-key solutions will include front-of-line (FOL) and end-of-line (EOL) capability from wafer handling, back-grinding, and dicing with KGD traceability thru the embedded chip process, frame/strip singulation, FT, marking pack & ship providing additional 30% cost reduction in the future. Here's an illustration of Embedded Technology Roadmap and Product Platforms.

Embedding Mosfets

A new technology that uses chip embedding of power MOSFETs in PCBs can meet increasing requirements for electrical power management systems

Chip Embedding of Power Semiconductors in Power Ciruit Boards

Chip Embedding of Power Semiconductors in Power Ciruit Boards

Design and demonstration of Glass Panel Embedding for 3D System Packages for heterogeneous integration applications

Abstract This paper demonstrates a next generation high-performance 3D packaging architecture with smaller form factor, excellent electrical performance and reliability for heterogeneous integration. High density Logic-HBM integration, today, is built predominantly using interposers which are fundamentally limited in assembly pitch and interconnect lengths, and they also are expensive as the package sizes increase. On the other hand, high-frequency applications continue to use laminates which are again limited by package size and ability to integrate many components. WLFO promises better performance and form factor at lower costs, but current WLFO packages are mold-based and hence are limited to small packages. This paper presents the first demonstration of 3D Glass Panel Embedding (GPE) technology for high-performance large package applications involving heterogeneous integration. The tailorable CTE of glass allows a reliable direct board SMT of large GPE packages that not only benefits form factor and signal speed, but also provides radical benefits to power delivery. Unlike interposers and silicon bridges, GPE packages are not bump limited and can support BEOL-like I/O densities with Silicon-like RDL at much lower costs. The fundamental limitations like die-shift and poor dimensional stability of current organic WLFO packages are addressed by parametric process improvements to reduce die-shift to <2 um while also improving the RDL surface planarity for high-yielding fine-line structures. This paper describes the fabrication process for 3D GPE, leading to demonstration of a technology using embedding of chips with all-Cu interconnections at 40um I/O pitch while also enabling double-side assembly of chips to achieve 3 levels of device integration.

Humidity and temperature sensor system demonstrator with NFC tag for HySiF applications

Abstract. Hybrid System-in-Foil (HySiF) is one of the emerging branches of flexible electronics in which ultra-thin silicon chips are integrated with flexible sensors in polymeric foils (Elsobky et al., 2018; Alavi et al., 2018). Intensive attention was given to the implementation of flexible environmental sensing platforms for logistics and food packaging (Cartasegna et al., 2011; Liu et al., 2016). The aim of this work is the implementation of a sensor system demonstrator using HySiF components, namely an ultra-thin microcontroller chip in addition to an on-chip temperature and an on-foil humidity sensors. The measurement concept for the relative humidity sensor is measuring the capacitance difference between an off-chip (on the foil substrate) humidity dependent sensor capacitor, and another humidity independent reference capacitor. The electrical readout technique is based on the charge amplifier switched capacitor circuit. It is implemented using a commercially available microcontroller (EM microelectronics EM6819) which has the advantage of being available as single chips to enable post-processing steps such as backthining and chip embedding in a thin polymer package. Sensor and reference capacitors are homogeneously integrated on-foil. 400 and 30 µm thick microcontroller dies (MCU) are used in this application. The charge amplifier result is digitized using an internal 10-bit analog-to-digital converter (ADC). The 10-bit ADC is time multiplexed between the charge amplifier structure and the internal temperature sensor. Linear interpolation is used to fit the digital output of the ADC and calibrate the output of the sensor system. Readings of the humidity level and the temperature are written to an NFC tag (from the company EM microelectronics based on chip EM NF4) using the contact interface. Readings can be accessed using a customized android application on a smartphone.

Adaptive Layout Technique for Microhybrid Integration of Chip-Film Patch

In this paper, a unique adaptive layout methodology for accurate interconnection between two or more functional chips at the wafer level is presented. The methodology is based on an automatic layout modification for each embedded chip with considering exact related offset and rotation after chip embedding. As a result, a wafer-level embedding and accurate interconnecting and integrating of ultrathin chips in the polymer are feasible. The significant application of the presented accurate interconnection between the groups of functional chips is the microhybrid system-in-foil. Also, an adaptive interconnect layout at wafer-level base, allowing for a small wire pitch on and off the chip, leads to reducing silicon area and, thus, saves cost. In this paper, the process flow for embedding and integrating chips based on the adaptive layout technique is presented. The custom designed test chips are processed for the measurement and optimization of overlay accuracy of the adaptive interconnect layout regardless of the chip thickness, warpage, and topography. Besides, the electrical measurements after integrating ultrathin chips in foil confirm the interconnection between chips.

A novel wet etching based double-sides interposer structure with deep trenches for 3-D hetero-integration

Through-silicon-via (TSV) interposer has been proved to be a good solution for three-dimensional integration to achieve high density and improved performance. In this paper, a novel double-sides silicon interposer structure with deep trenches was proposed to achieve high density 3-D hetero-integration. The TSVs in the interposer were fabricated by wet etching method on both sides, which has low cost, good reliability and suitable for batch production. In order to minimize the TSV size and provide a higher interconnect density as well as retain the mechanical reliabilities of the interposer, deep trenches were wet-etched before TSV fabrication, which were also used for chip embedding. To further increase the integration density, multiple interconnects were attempted to be deposited in a single TSV and their electrical properties were systematically characterized.

Highly efficient isolation and release of circulating tumor cells based on size-dependent filtration and degradable ZnO nanorods substrate in a wedge-shaped microfluidic chip.

Circulating tumor cells (CTCs) have been regarded as the major cause of metastasis, holding significant insights for tumor diagnosis and treatment. Although many efforts have been made to develop methods for CTC isolation and release in microfluidic system, it remains significant challenges to realize highly efficient isolation and gentle release of CTCs for further cellular and bio-molecular analyses. In this study, we demonstrate a novel method for CTC isolation and release using a simple wedge-shaped microfluidic chip embedding degradable znic oxide nanorods (ZnNRs) substrate. By integrating size-dependent filtration with degradable nanostructured substrate, the capture efficiencies over 87.5% were achieved for SKBR3, PC3, HepG2 and A549 cancer cells spiked in healthy blood sample with the flow rate of 100μL min-1. By dissolving ZnNRs substrate with an extremely low concentration of phosphoric acid (12.5mM), up to 85.6% of the captured SKBR3 cells were released after reverse injection with flow rate of 100μL min-1 for 15min, which exhibited around 73.6% cell viability within 1h after release to around 93.9% after re-cultured for 3days. It is conceivable that our microfluidic device has great potentials in carrying on cell-based biomedical studies and guiding individualized treatment in the future.

Next Generation Chip Embedding Technology for High Efficient Mid Power Modules

Abstract Embedding active dies into the substrate is fulfilling integration requirements for modern communication devices, and furthermore embedding was shown to have beneficial effects on electrical performance and thermal dissipation, especially for mid power modules (from a few hundred watts to 5kW) [1–3]. It comes with strong advantages as the power modules operate at higher frequencies (MHz range) and aim to apply smaller capacitors and inductors. This approach reduces the overall PCB size and weight from system point of view. These beneficial effects were observed especially for embedded power dies that were already mounted in a lead frame cavity when embedding [3]. In this paper we shall report the development of embedded technologies for power modules mounted in a lead frame cavity and compare electrical performance, thermal dissipation and reliability results with conventional PQFN packaging [3]. We shall also report electrical performance in various operation frequency ranges from a few kHz to MHz to address the benefit on high switching frequency power modules for SiC or GaN applications. We will also address if the EMI effect can be eliminated by using chip embedded technology instead of wire bonding connection from driver to gate pad of power MOSFET chip. We will conclude that the challenges of electrical performance and thermal dissipation required for today's power modules can successfully be overcome by next generation power modules based on lead frame chip embedding.

Higher Efficiency Power Module Solutions by Chip Embedding

Abstract The development in communication handheld devices has pushed the demand for packages with high level of functionality and complexity at the same time smaller package outline and decreased package thickness. Embedding active dies and/or passive components into the substrate is fulfilling these integration requirements, but embedding can have further beneficial effects (electrical performance, thermal dissipation, shielding) that deliver more benefit for embedding (1). Whereas embedding dies in substrates seems a simple concept, it can come with strong advantages as found in the described case for Power Modules in terms of electrical performance and thermal dissipation. In this paper we shall report the development of embedded technologies for Power Modules and compare electrical performance, thermal dissipation and reliability results with other Power Module package types. We shall report on an intelligent power module for server applications up to 1.5kW consisting of a driver IC and 2 MOSFETs using embedded die in substrate technology in high volume manufacturing. We will describe the development of next generation embedding technologies for Power Modules, their expected benefits and respective application targets together with simulation results. We conclude with a brief overview of the challenges that come with embedded packaging supply chain.