Chip Embedding Research Articles

Electrical characteristics and reliability performance of IGBT power device packaging by chip embedding technology

With the current high demand for energy saving and low power consumption, numerous studies have been conducted to meet this requirement. Higher switch efficiency is one of the factors for power saving in power inverters and converters. Among the methods for improved switch efficiency, the modified package structure is one of the solutions. An embedded power module enables shortened transmitting routes and lower parasitic reactions, suggesting better power switching performance. Meanwhile, embedding allows the power devices to integrate active or passive devices above or beneath a component, leading to a three-dimensional packaging structure. This feature is also applicable in the integration of power devices because of its double side contact structure. Four dies that contain two insulated gate bipolar transistors and two diodes in this study were embedded and integrated in a carrier substrate to produce a next-generation power inverter module. The process began by attaching a die on a Cu lead frame by a SAC305 solder paste. This is followed by a lamination process to form a built-up dielectric layer on the Cu lead frame. The conducting vias and circuits were formed on the built-up dielectric layer by a UV laser and were metalized with sputtered seed layer and electroplating. The circuit layout can be revealed with subsequent etching processes by hatching another layer of electroplated Sn using UV laser. Finally, a layer of solder mask was printed to prevent electric shock on the surface layer. Structure and process features are discussed, and electrical testing and reliability tests are conducted in this paper.

Embedded Power Modules – A new approach using Power Core and High Power PCB

Power electronics packaging applications has strong demands regarding reliability and cost. The fields of developments reach from low power converter modules, over single or multichip MOSFET or IGBT packages, up to high power applications, like needed e.g. for solar inverters and automotive applications. This paper will give an overview about these applications and a description of each ones demand. The spectrum of conventional power electronics packaging reaches from SMD packages for power chips to large power modules. In most of these packages the power semiconductors are connected by bond wires, resulting in large resistances and parasitic inductance. Additionally bond wires result in a high stray inductance which limits the switching frequency. The embedding of chips using Printed Circuit Board (PCB) technology offers a solution for many of the problems in power packaging. This paper will show today's available power packages and power modules, realized in industrial production as well as in European research projects. All technologies which are used are based on PCB materials and processes. Chips are mounted to Cu foils, lead frames, high power PCBs or even ceramic substrates, embedded by vacuum lamination of laminate sheets and electrically connected by laser drilling and Cu plating. A new approach for embedded power modules will be presented in detail. In this project, different application fields are covered, ranging from 50 W over 500 W to 50kW power modules for different applications like single chip packages, over power control units for pedelec (Pedal Electric Cycle), to inverter modules for automotive applications. This approach will focus on a power core base structure for the embedded semiconductor, which is then connected to a high power PCB. The connection to the embedded die is realized by direct copper connection only. The technology principle will be described in detail. Frist manufactured demonstrators will be presented. The presented new approach for the realization of a power core structure offers new possibilities for the module manufacturing, avoiding soldering or Ag sintering of the power semiconductors and the handling of thick copper substrates during the embedding process.

Innovative and Reliable Power Modules: A Future Trend and Evolution of Technologies

Since the introduction of the first power module by Semikron in 1975, many innovations have been made to improve the thermal, electrical, and mechanical performance of power modules. These innovations in packaging technology focus on the enhancement of the heat dissipation and thermal cycling capability of the modules. Thermal cycles, caused by varying load and environmental operating conditions, induce high mechanical stress in the interconnection layers of the power module due to the different coefficients of thermal expansion (CTE), leading to fatigue and growth of microcracks in the bonding materials. As a result, the lifetime of power modules can be severely limited in practical applications. Furthermore, to reduce the size and weight of converters, the semiconductors are being operated at higher junction temperatures. Higher temperatures are especially of great interest for use of wide-?bandgap materials, such as SiC and GaN, because these materials leverage their material characteristics, particularly at higher temperatures. To satisfy these tightened requirements, on the one hand, conventional power modules, i.e., direct bonded Cu (DBC)-based systems with bond wire contacts, have been further improved. On the other hand, alternative packaging techniques, e.g., chip embedding into printed circuit boards (PCBs) and power module packaging based on the selective laser melting (SLM) technique, have been developed, which might constitute an alternative to conventional power modules in certain applications.

The Application and Prospects of SOPC Technology in Image-Processing

The real-time image-processing by SOPC technology on the hardware is the new direction of the image-processing technology. FPGA is the core component of the image-processing based on SOPC technology. The principles and characteristics of SOPC technology and the commonly image-processing algorithm are introduced in the first part. Then the traditional DSP image-processing technology is compared with the image-processing technology using FPGA chip embedding with the Nios II soft-core processor. As a result, a conclusion that the usage of the SOPC technology can increase the speed and working frequency of image-processing is derived. At last, the application status of SOPC technology used in image-processing is introduced. It can be concluded that the SOPC technology in real-time image-processing have the broad application prospect.

Site-specific metrology, inspection, and failure analysis of three-dimensional interconnects using focused ion beam technology

Today three-dimensional system-in-package integration together with advanced interconnect technologies based on through silicon vias, through encapsulant vias, and microbumps are considered some of the most promising enabling technologies for “More than Moore” solutions. These technologies involve vertical die stacking or chip embedding with high-density interconnects and are based on combinations of process steps that come from formerly strictly separated technology areas. Thus, there is an increasing need to understand a large number of different interface properties, to control and optimize processes, and to avoid defect formation that could affect reliability. This complexity, in terms of design, new materials, and material combinations, also requires the development of new failure analysis tools to support these developments. The application potential of a new fast plasma focused ion beam (FIB) system for metrology and failure analysis is demonstrated in several selected case studies. The higher material removal rate of this system improves the range of application fields and/or the analysis throughput. This makes the plasma-FIB a very attractive tool for the analysis of relatively large interconnect structures without any need for mechanical preparation steps.

Next Generation High Power Electronic Modules Based on Embedded Power Semiconductors

The spectrum of conventional power electronics packaging reaches from SMD packages for power chips to large power modules. In most of these packages the power semiconductors are connected by bond wires, resulting in large resistances and parasitic inductances. Power chip packages have to carry semiconductors with increasing current densities. Conventional wire bonds are limiting their performance. Today's power modules are based on DCB (Direct Copper bonded) ceramic substrates. IGBT switches are mounted onto the ceramic and their top side contacts are connected by thick Al wires. This allows one wiring layer only and makes an integration of driver chips very difficult. Additionally bond wires result in a high stray inductance which limits the switching frequency. Especially for the use of ultra-fast switching semiconductors, like SiC and GaN, it is very difficult to realize low inductive packages. The embedding of chips offers a solution for many of the problems in power chip packages and power modules. While chip embedding was an academic exercise a decade ago, it is now an industrial solution. A huge advantage of packaging using PCB technology is the cost-effective processing on large panel. Furthermore embedded packages and modules allow either double-side cooling or 3D assembly of components like capacitors, gate drivers or controllers. The advanced results of research projects will be discussed in the paper. An ultra-low inductance power module with SiC switches at 20 A / 600 V has been realized and characterized. The DC link inductance of the module was 0,8 nH only. These results sparked a huge interest in currently starting follow up projects creating package for fast switches. In a further project power modules for automotive power inverters for motor control are under development. As a project demonstrator, a 10 kW module with IGBTs and diodes at 400 V / 500 A, was manufactured. This demonstrator is based on high power PCB technology and was fully characterized; the results will be presented in detail. Recently started research projects will face the challenges of MW solar inverters at 1000 A and 1000 V, using SiC semiconductors as switches. First concepts will be presented as an outlook.

Multichip Embedding Technology Using Fine-Pitch Cu–Cu Interconnections

Increasing performance and functional density while maintaining low cost is a catalyst for technological progress in the field of packaging. From flip-chip with solder to a hybrid approach of copper and solder, many methods have been created to reach this objective. The 3-D Packaging Research Center at Georgia Tech has been revolutionizing interconnection technology with the multichip embedding chip-last approach, which utilizes ultrathin adhesive-bonded copper bumps to enable ultrafine-pitch chip-to-package interconnections. This technology has been proven to be highly reliable using a low-cost low-temperature direct copper-to-copper bonding approach at 30-μm pitch and ~20-μm standoff height copper-to-copper interconnections. This interconnection method provides a platform for integration with flip-chip packages through its proven ability to work well with different die sizes and thicknesses bonded to the surface of ultrathin organic substrates. The next step in advancing the chip-last approach is to investigate chip embedding at the single-chip and multichip levels. Consequently, this paper focuses on: 1) the design and fabrication of the test vehicle to examine the reliability of the previously demonstrated copper-to-copper interconnections after embedding a thin die in an organic substrate, and 2) assembly process development and reliability data for the interconnections. Specifically, advances in the assembly process include: 1) a novel method to perform chip-last assembly at the panel level leading to a 10-15 times reduction in assembly time per die, and 2) an improved two-step assembly process to achieve simultaneous die embedding and cavity planarization. This embedding technology and its advancements not only allow actives to be embedded in organic substrates but also enables higher functional integration at high-throughput, making chip-last adhesive bonding with low-profile copper-to-copper interconnections a robust chip embedding solution for the next generation of highly integrated heterogeneous subsystems.

Active and passive component embedding into low-cost plastic substrates aimed at smart system applications

The technology development for a low-cost, roll-to-roll compatible chip embedding process is described in this paper. Target applications are intelligent labels and disposable sensor patches. Two generations of the technology are depicted. In the first version of the embedding technology, the chips are embedded in an adhesive layer between a copper foil and a PET film. While this results in a very thin (< 200 μm) and flexible system, the single-layer routing and the incompatibility with passive components restricts the application of this first generation. The double-sided circuitry embedding technology is an extension of the single-sided, foil-based chip embedding, where the PET film is replaced by a second metal foil. To obtain sufficient mechanical strength and to further reduce cost, the adhesive film is replaced by a substrate material which is compatible with the chip embedding concept. Both versions of the foil-based embedding technology are very versatile, as they are compatible with a broad range of polymer materials, for which the specifications can be tuned to the final application.

High Yield Embedding of 30μm Thin Chips in a Flexible PCB using a Photopatternable Polyimide based Ultra-Thin Chip Package (UTCP)

A thin chip package for off-the-shelf ICs is developed which enables the embedding of these chips into a flexible circuit board. The package consists of a copper fan-out on a polyimide substrate, in which the thinned IC (30μm) is embedded. These packages are subsequently integrated in a standard flexible circuit board (FCB). A microcontroller and a proprietary DSP processor are embedded using this technology. The yield of the Ultra-Thin Chip package (UTCP) was measured before embedding in the circuit board, and reaches up to 87% for the packaged microcontrollers (MSP430 family, known-good dies). The yield on the DSP processor was measured to be 62%. After embedding in the FCB, 95% of the functional UTCP-packaged dies are still functional.

Next Generation eWLB (Embedded Wafer Level BGA): Advanced 3D SiP Packaging Solution

Current and future demands of mobile/portable electronic systems in terms of performance, power consumption, reliable system at a reasonable price are met by developing advanced/appropriate silicon process technology, innovative packaging solutions with use of chip-package-system co-design, low cost materials, advanced assembly and reliable interconnect technologies. In this article packaging evolution for hand held application is discussed with special focus on next generation chip embedding technology called eWLB in detail. To meet the above said challenges eWLB was developed which offers additional space for routing higher I/O chips on top of Silicon chip area which is not possible in conventional WLP or WLB. It also offers comparatively better electrical, thermal and reliability performance at reduced cost with possibility to address more Moore [decreasing technology nodes with low-k dielectrics in SoC] and more than Moore [heterogeneous integration of chips with different wafer technology as SiP solution in multi die or 3D eWLB approaches]. Currently 1st generation eWLB technology is available in the industry with 200mm and 300mm carrier size. This paper will highlight some of the recent advancements in progress development and mechnical characterization in component level and board level reliaiblity of next generation eWLB technologies of double-side 3D eWLB. Standard JEDEC tests were carried out to investigate component level reliability and both destructive/non-destructive analysis was performed to investigate potential structural defects. Daisychain Test vehicles were prepared and also tested for drop and TcoB (Temperature on Board) reliaiblity in industry standard test conditions. There was significant improvement of characteristic lifetime with thined eWLB in TcoB performance because of its enhanced flexibility of package. And there was study of board level reliabiilty with underfill in SMT for large size eWLB packages. This paper will also present study of package warpage behavior with temperature profile as well as failure analysis with microsturctural observation for comprehensive understanding of mechanical behavior of next generation eWLBs.

Ultrathin Optoelectronic Device Packaging in Flexible Carriers

This paper presents the development of an advanced packaging technique for commercially available optoelectronic devices. Vertical cavity surface emitting laser (VCSEL) diodes and photodiodes are thinned down to 20 μm thickness, and are embedded in flexible carriers, resulting in a 75-μm-thin package, which can be bent down to a bending radius of 2 mm. Electrical, optical, and mechanical characterization addresses the influence of thinning and embedding of bare optoelectronic chips on their main properties. Next to the embedded optoelectronics, also electrical ICs like amplifiers and drivers can be housed in the same thin flexible package, using an identical technology and layer build-up. Finally, this new packaging approach is demonstrated in two different integrated sensor applications and in an integrated optical interconnection. For the latter application, also waveguides and optical out-of-plane coupling elements are integrated in the package and the complete system reliability is assessed by accelerated aging tests.

Design and implementation of flexible and stretchable systems

This paper presents a summary of the modeling and technology developments for flexible and stretchable electronics. These technologies can achieve mechanically bendable and stretchable subsystems by incorporating the electronic circuit into a matrix made of a soft polymer. The base substrate used for the fabrication of flexible circuits is a uniform polyimide layer, while silicones or polyurethanes materials are preferred for the stretchable circuits. The method developed for chip embedding and interconnections is named Ultra Thin Chip Package (UTCP). Extensions of this technology can be achieved by stacking and embedding thin dies in polyimide, providing large benefits in electrical performance and still allowing some mechanical flexibility. These flexible circuits can be converted into stretchable circuits by replacing the polyimide by a soft and elastic silicone material. The integration of ultra thin dies at package level, with thickness in the range of 10–30 μm, into flexible and/or stretchable materials are demonstrated. Furthermore, the design and reliability test of stretchable metal interconnections at board level are analyzed by both experiments and finite element modeling. We have shown through finite element modeling and experimental validation that an appropriate thermo-mechanical design is necessary to achieve mechanically reliable circuits and thermally optimized packages.

Realization of Power Modules by Chip Embedding Technology

The continuous miniaturization of silicon dies and the need for a further package size reduction, with an equal or better performance and reduced manufacturing cost, are the main drivers for new packaging concepts. The embedding of active and passive components offers a wide range of benefits and potentials. With the use of laminate based technology concepts, components can be moved from surface mount into the build-up layers of substrates by embedding and by that, the third dimension will be available for further layers or assemblies. This paper will briefly discuss the necessary process steps of the embedded chip technology, which is based on printed circuit board manufacturing processes, and will also demonstrate the transfer of the technology from a smaller size lab scale equipment environment to an industrial comparable process line, capable of processing large panel formats up to 18” x 24”. The paper will also briefly describe this development and categorize today's embedding technologies. First modules with embedded chips are in production in Asia, mainly for telecom and computer applications. In Europe embedding has gained a strong interest for power modules, especially in automotive applications. Main drivers are the capability for compact and thin packaging, the high reliability and cost saving potential. In a number of European cooperation projects with partners from industry and research, embedding of power chips, like IGBTS and power MOSFET, is of high interest. In this paper current achievements of these projects will be shown, especially examples of realized devices and their characteristics. The dominating technology for power chip embedding is a face-up technology. Chips are bonded with their backside (drain contact) to a Cu substrate using highly conductive adhesive or solder. Using the face up assembly, a direct contact to the backside of the die is possible, allowing a lot of benefits for driving high currents and applying an efficient thermal management for the power devices. Then Chips are embedded by vacuum lamination of prepreg or RCC (resin coated copper) layers. Via holes to the top contacts (gate and source) are formed by laser drilling. The vias are metallized using conventional Cu plating. Finally conductor structures are etched in the top Cu layer, finalizing the circuit. Details will be given about device manufacturing, related yield issues and strategies to overcome them. Finally scenarios for the implementation of embedding technology and concepts for future applications will be discussed.

3D-stacking of UTCPs as a module miniaturization technology

3D-stacking of Ultra Thin Chip Packages (UTCP’s) – one of the emerging technologies in the field of high density integration - is presented here. This technology is developed to increase the functionality of the electronic devices and to raise the comfort zone by reducing the overall size and weight of the package. This has a bright future in the area of mobile communication, medical equipments like hearing aids, implants, patient monitoring. This paper describes an approach to produce miniaturized modular packages by using Ultrathin Chip Package Technology, stacking and through-hole (TH) interconnection technology. UTCP technology is a board level packaging concept, based on embedding of ultra-thin chips (∼20 μm) within two 20 μm thick spin-on polyimide layers resulting in a thin flexible chip package of thickness ∼50 μm. Stacking of the 4 layers of UTCPs by using 25 μm thick layers of adhesive films and vacuum lamination processes results in stacked UTCP modules of total thickness ∼300 μm. The connection to the different layers of the UTCPs is realized by drilling THs on the outer contact pads on the stacked packages, followed by metallization of these THs by Cu electroless deposition, electroplating and finally metal structuring. After processing and testing, the stacks can be easily mounted within functional demonstrators (e.g, Hearing Aid device, etc) replacing single silicon die of almost same size, but with 4 times output.

Design and characterisation of an AES chip embedding countermeasures

In critical communication infrastructures, hardware accelerators are often used to speed up cryptographic calculations. Their resistance to physical attacks determines how secure the overall infrastructure is. In this paper, we describe the implementation and characterisation of an AES accelerator embedding security features against physical attacks. This AES chip is implemented in HCMOS9gp 130 nm STM technology. The countermeasure is based on duplication and works on complemented values in parallel. The chip was tested against side channel attacks showing the efficiency of the proposed countermeasure against such attacks. Fault injection tests based on the use of local laser shoots showed that the fault detection mechanism did indeed react as expected. However, using clock set-up time violations, 80% of the secret key were retrieved in less than 40 hours, thus illustrating the limits of the duplication countermeasure against a global fault attack which was published after the chip was designed.

Next Generation System in a Package Manufacturing by Embedded Chip Technologies

The embedding of active and passive components offers a wide range of benefits and potentials. With the use of laminate based technology concepts, components can be moved from surface mount into the build-up layers of substrates by embedding and thereby the third dimension will be available for further layers or assemblies. This paper will briefly discuss the necessary process steps of the embedded chip technology and more importantly it will focus on new efforts to actually use chip embedding concepts for the realization of standard-type industrial quad flat packages with embedded chips (embedded chip QFN). Chips of 50 μm thickness, a pad pitch of 100 μm, and pad size of 85 μm are die bonded to a copper substrate and subsequently embedded in RCC (resin coated copper) layers by using vacuum lamination. The resulting QFN packages are only 160 μm thick and provide standard pads at 400 μm pitch and a total number of 84 I/Os with dimensions of 10 × 10 mm2. All embedded chip QFN packages at the prototype level are manufactured in 250 × 300 mm2 panels.

Chip Embedding for Printed Circuit Boards and Subsystems

The reason for chip embedding by means of PCB technology are manifold. Actually there are several emerging technologies on the market which all face one common problem: To realize the escape routing of a high pin count die one has to use several build up layers or very fine lines & spaces for the PCB. Both approaches have a significant influence on the cost of a electrical component because both solutions raise the manufacturing complexity. Due to this problem approaches like “chip first” or “chip last” are being discussed in plenty of papers. With this paper, an alternative way of producing embedded systems is mentioned, which overcomes many of the actual problems.

Next Generation System in a Package Manufacturing by Embedded Chip Technologies

The embedding of active and passive components offers a wide range of benefits and potentials. With the use of laminate based technology concepts, components can be moved from surface mount into the build-up layers of substrates by embedding and by that, the third dimension will be available for further layers or assemblies. This paper will briefly discuss the necessary process steps of the embedded chip technology and more importantly it will focus on new efforts to actually use chip embedding concepts for the realization of standard-type industrial Quad Flat Packages with embedded chips (embedded chip QFN). Chips of 50 μm thickness, a pad pitch of 100 μm and pad size of 85 μm are die bonded to a copper substrate and subsequently embedded in RCC (Resin-Coated-Copper) layers by using vacuum lamination. The resulting QFN packages are only 160 μm thick and provide standard pads at 400 μm pitch and a total number of 84 I/Os with dimensions of 10x10 mm2. All embedded chip QFN packages at prototype level are manufactured in 250x300 mm2 panels. The present work will include QFN package reliability results after extensive testing of thermal cycling, temperature humidity, high temperature storage and pressure cooker test. The investigation of new embedding material combinations is one task to provide a reliable package. The main focus here is on new materials that offer improved package stability and also the ability to embed dies of different thickness. Together with material suppliers improved resin formulations as well as the introduction of filler and glass fibers into the resin layers is currently realized and tested. In order to realize a further miniaturization ultra fine pitch (UFP) and fine line (UFL) approaches will be presented. For a UFP approach the goal is to develop the laser via technology further towards their limits as well as the investigation of new concepts. UFP requires the use of a semi additive patterning process. Here LDI processing is being used for all new generation chip embedded packages due to its potential for very fine copper patterning. Results on very fine L/S of 15–20μm will be shown based on the semi-additive processes on an ultra thin initial 1–2μm copper foil. Finally different applications will be presented. In an industrial cooperation different power package developments are ongoing. Here single and multi chips modules are realized as well as multiple routing layers. The combination of power and logic is one of the main challenges here, due to the need of thick copper layers for the power part and the more fine pitch demands for the controller chips. Process developments and results will be discussed in detail.

Call for Papers—Special Issue: Organizing for Innovation in the Digitized World

Background Rapid developments in digital technology have brought several challenges in innovation research. First, digital technology has radically reduced the communication cost for remote collaboration and coordination, which has led to the emergence of new organizing structures that transcend the traditional organizational boundaries and space limitations. Open innovation, for example, allows organizations to tap into a much broader source of new ideas by democratizing the innovation process and taking advantage of reduced communication cost and access to shared digital resources. By overcoming constraints on communication and coordination, the use of digital technology has enabled organizations to radically decentralize the way they manage innovation across networks of increasingly heterogeneous actors. Examples of such networked, distributed innovation abound: from software engineering companies that work with the global hacker community to improve their software, to manufacturing companies sourcing innovation from customers and suppliers, to mass media companies drawing on digital content created by users. Second, change in the innovation process is also taking place due to digital convergence. The integration and embedding of digital technologies into nondigital artifacts is opening up vast new avenues for radical innovation. Integration of digital technologies, often in the form of computing, memory, and transmission capability, not only allows the products and services to become “smarter,” but also potentially transform the way the products are consumed and experienced. The embedding of global position systems chips and radio frequency identification tags into ordinary products, for example, enables the production of streams of digital data that can be combined with other forms of digital information— such as digital map on Google Earth or social networks on MySpace.com. Therefore, the notion of digital convergence that is often used to describe the bundling of phone, Internet, mobile, and TV services need to be expanded to all forms of artifact design, process change, and experience creation to theorize about these kinds of “radical” digital innovations. Radical digital convergence blurs the boundaries across industries and commerce, as exemplified by the collaboration between Apple and Nike when they introduced Nike shoes that interact with iPods. Here, organizations are confronted with heterogeneous knowledge resources that are often embedded in different pockets of the organizational hierarchy. Third, the advances in digital technologies and software platforms now allow organizations to “digitize” multiple aspects of work processes that were previously supported by analogue tools. Digitized work practices can be modularized, integrated, and reconfigured. In the construction industry, for example, building information management systems have started to leverage new kinds of digital information infrastructures that integrate activities related to design, budgeting, scheduling, material management, and human resources. Again, we see the challenge of managing heterogeneity across organizational borders as a result of digital innovation. We believe these and many other challenges related to rapid and radical digitization will dominate the concerns of managers in this century. Studying the full impact of digital technology on innovation, however, requires genuine cross-disciplinary dialogue. Given the novelty and speed of this phenomenon, we need richer vocabularies, diverse theoretical perspectives, new research methodologies, and novel data analysis techniques allowed by access to digital data and traces. We also need to increase the breadth of research as the impact of digital technologies can be found in many different industries,

Embedding and assembly of ultrathin chips in multilayer flex boards

Purpose – The purpose of this paper is to present results from the EC funded project SHIFT (Smart High Integration Flex Technologies) on the embedding in and the assembly on flex substrates of ultrathin chips.Design/methodology/approach – Methods to embed chips in flex include flip‐chip assembly and subsequent lamination, or the construction of a separate ultra‐thin chip package (UTCP) using spin‐on polyimides and thin‐film metallisation technology. Thinning and separation of the chips is done using a “dicing‐by‐thinning” method.Findings – The feasibility of both chip embedding methods has been demonstrated, as well as that of the chip thinning method. Lamination of four layers of flex with ultrathin chips could be achieved without chip breakage. The UTCP technology results in a 60 μm package where also the 20 μm thick chip is bendable.Research limitations/implications – Further development work includes reliability testing, embedding of the UTCP in conventional flex, and construction of functional demons...