Next Generation System in a Package Manufacturing by Embedded Chip Technologies

Abstract

The embedding of active and passive components offers a wide range of benefits and potentials. With the use of laminate based technology concepts, components can be moved from surface mount into the build-up layers of substrates by embedding and by that, the third dimension will be available for further layers or assemblies. This paper will briefly discuss the necessary process steps of the embedded chip technology and more importantly it will focus on new efforts to actually use chip embedding concepts for the realization of standard-type industrial Quad Flat Packages with embedded chips (embedded chip QFN). Chips of 50 μm thickness, a pad pitch of 100 μm and pad size of 85 μm are die bonded to a copper substrate and subsequently embedded in RCC (Resin-Coated-Copper) layers by using vacuum lamination. The resulting QFN packages are only 160 μm thick and provide standard pads at 400 μm pitch and a total number of 84 I/Os with dimensions of 10x10 mm2. All embedded chip QFN packages at prototype level are manufactured in 250x300 mm2 panels. The present work will include QFN package reliability results after extensive testing of thermal cycling, temperature humidity, high temperature storage and pressure cooker test. The investigation of new embedding material combinations is one task to provide a reliable package. The main focus here is on new materials that offer improved package stability and also the ability to embed dies of different thickness. Together with material suppliers improved resin formulations as well as the introduction of filler and glass fibers into the resin layers is currently realized and tested. In order to realize a further miniaturization ultra fine pitch (UFP) and fine line (UFL) approaches will be presented. For a UFP approach the goal is to develop the laser via technology further towards their limits as well as the investigation of new concepts. UFP requires the use of a semi additive patterning process. Here LDI processing is being used for all new generation chip embedded packages due to its potential for very fine copper patterning. Results on very fine L/S of 15–20μm will be shown based on the semi-additive processes on an ultra thin initial 1–2μm copper foil. Finally different applications will be presented. In an industrial cooperation different power package developments are ongoing. Here single and multi chips modules are realized as well as multiple routing layers. The combination of power and logic is one of the main challenges here, due to the need of thick copper layers for the power part and the more fine pitch demands for the controller chips. Process developments and results will be discussed in detail.