Chip-Package-Board Reliability of System-in-Package Using Laminate Chip Embedding Technology Based on Cu Leadframe

Abstract

We investigate the reliability of a system-in-package (SiP) technology, which uses laminate chip embedding based on a copper leadframe. For this SiP technology, we apply different Si-based transistor technologies. We test the reliability of three types of chip-embedded packages: a single-chip embedded package (SCP) with an embedded MOSFET test chip for basic understanding, and two SiPs—a multichip embedded package (MCP) with a dc/dc converter for industrial applications and a SiP for lighting applications. In order to better represent specific field stresses for the target applications, we develop and investigate new test methods for laminate-based packages. In this article, we report the design, the implementation, and the results of those new methods and discuss their benefits and validity. We conducted conventional test methods like temperature humidity bias (THB) for comparison. The results of all these tests demonstrate a very good reliability of the chip-embedded packages. We also investigate early damages inside the packages using failure analysis techniques such as cross sectioning. The cooperation of partners along the value chain resulted in a coherent understanding of chip-package-board material aspects and design for reliability.