Carry Select Adder Research Articles

Design Efficient Vedic-Multiplier for Floating-Point MAC Module

Multiplication-accumulation (MAC) operation plays a crucial role in digital signal processing (DSP) applications, such as image convolution and filters, especially when performed on floating-point numbers to achieve high-level of accuracy. The performance of MAC module highly relies upon the performance of the multiplier utilized. This work offers a distinctive and efficient floating-point Vedic multiplier (VM) called adjusted-VM (AVM) to be utilized in MAC module to meet modern DSP demands. The proposed AVM is based on Urdhva-Tiryakbhyam-Sutra (UT-Sutra) approach and utilizes an enhanced design for the Brent-Kung carry-select adder (EBK-CSLA) to generate the final product. A (6*6)-bit AVM is designed first, then, it is extended to design (12*12)-bit AVM which in turns, utilized to design (24*24)-bit AVM. Moreover, the pipelining concept is used to optimize the speed of the offered (24*24)-bit AVM design. The proposed (24*24)-bit AVM can be used to achieve efficient multiplication for mantissa part in binary single-precision (BSP) floating-point MAC module. The proposed AVM architectures are modeled in VHDL, simulated, and synthesized by Xilinx-ISE14.7 tool using several FPGA families. The implementation results demonstrated a noticeable reduction in delay and area occupation by 33.16% and 42.42%, respectively compared with the most recent existing unpipelined design, and a reduction in delay of 44.78% compared with the existing pipelined design.

Implementation of Carry Skip Adder using Carry Select Adder with Improved Area, Delay, and Power Efficiency

This paper presented a Carry Skip Adder (CSKA) structure with less area, less delay, and lower power consumption. This can be achieved with Carry Select Adder's (CSLA) help. The proposed structure uses AND-OR-INVERT (AOI) and OR-AND- INVERT (OAI) compound gates for the skip logic. The use of Carry Select Adder will reduce the number of LUTs used (i.e.) the area of the proposed structure, reduce delay in performing processes, and also reduce power consumption. Simulation of the proposed hybrid CSKA-CSLA structure reveals a reduction in area, delay, and power consumption compared with the CSKA-RCA structure and with the latest works in the field. The simulation results reveal the improvementinareabyreducingthenumberofLUTsfrom91to79 and in delay by reducing the time required to process from 39.969ns to 35. 258ns and power consumption by reducing the power required to process from 64.44 mW to 64.41 mW when compared with the CSKA-RCA structure. This project used the Xilinx ISE tool to simulate the Area and Delay Analysis and the AlteraQuartusI Itool to simulate the Power Analysis.

Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation

In signal processing applications, the multipliers are essential component of arithmetic functional units in many applications, like digital signal processors, image/video processing, Machine Learning, Cryptography and Arithmetic & Logical units (ALU). In recent years, Profuse multipliers are there. In that, Vedic multiplier is one of the high-performance multiplications and it is used to signal/image processing applications. In order to ameliorate the performance of this multiplier further, by proposed a novel multiplier using hybrid compressor. The proposed hybrid compressor-based multiplier is designed and implemented in Field programmable Gate Array (FPGA—spartan 6). The synthesis result shows that the speed of proposed hybrid compressor-based multiplier gets improved as compared to Array multiplier (35.83%), Wallace tree multiplier (34.58%), Vedic Multiplier based on Carry look ahead adder (CLA) (28.49%), Vedic Multiplier based on Ripple carry adder (RCA) (20.65%), Booth Multiplication (21.65%) and Vedic Multiplication based on Han-Carlson Adder (HCA) (20.10%) and Hybrid multiplier using Carry Select Adder (CSELA) (17.81%) and Hybrid Vedic Multiplier (7.15%).

Power Efficient Implementation of ECC Using LCSLA Based Dual Field Vedic Multiplier

The Elliptic Curve Cryptographic (ECC) technique is employed for security standards such as Security Key Management (SKM), digital signature, data authentication and so on. The ECC technique is capable of sequential and parallel mode processes through a unified design. It is used for both equally binary fields and prime fields of cryptosystems. The DMM structure has been developed using CSA. This adder requires a greater amount of Full Adder circuits, which occupy more area. To overcome this problem, this paper discusses four different methods, such as DMM-Optimized Carry Look Ahead Adder, DMM-Optimized Carry Bypass Adder, DMM-Look up Table Carry Select Adder, and Dual Field Vedic Multiplier – LCSLA, which is used to increase the performance of the ECC. The parameters like power utilization, time delay information, and hardware area overhead are analyzed and compared with existing methods. Among those four methods, the DVM-LCSLA method gave better results in FPGA and ASIC performances.

Implementation of Area Efficient Carry Select Adder using Binary to Excess1 Code

Adders are widely used as essential parts in the design of digital integrated circuits. The Carry Select Adder (CSA) is unique among conventional adder topologies in that it operates quickly. There is a need for speedier arithmetic units as well as ones that use less power and take up less space as the mobile sector grows quickly. The Carry-Select method for adder design with carry propagation achieves a good trade-off between performance and cost. However, because it uses two ripple carry adders (RCA), the traditional CSA design still has a significant area overhead. A Binary to Excess-1 code converter (BE-1 converter) has been used in the development of a modified CSA design to overcome the issue. This study presents a practical method for reducing the size and power footprint of the CSA by introducing gate-level changes to the BE-1 converter design. Making use of this alteration, a 4-bit CSA architecture with a BE-1 converter is developed and contrasted with the industry standard CSA design. These designs are evaluated considering their area and power characteristics. The analytical results show that the suggested CSA structure is better than the traditional one and that using a CSA with a BE-1 converter is an efficient way to create a VLSI design.

An efficient in-memory carry select adder realization using resistive switching crossbar array with Ti-doped VO2 -based selector device

In-memory computing (IMC) can significantly increase speed efficiency by significantly reducing the time and energy consumption of memory access. Therefore, efficient storage actions are essential for applications that require a lot of data. This article presents a simple Carry Generation and Selection (CGS) scheme-based Carry SeLect Adder (CGS-CSLA) using the realization of the Boolean majority three operation with an overturned input in crossbar Resistive memory. However, the usage of crossbar array structure is constrained by the sneak current path issue in real applications. The proposed 1S1R crossbar array uses a Ti-doped VO2 selector device to address this problem. Also, the proposed CSLA comprises a multiple-step architecture that comprises numerous single-step elements to improve the speed of operation using parallel operations. The proposed CGS-CSLA removes the superfluous operations of the traditional CSLA by simplifying the logic. The suggested adder lowered the delay to 8+3log2(n) and used less energy by minimizing sneak currents.

Design and Implementation of High Speed 32-bit MAC Unit

Due to the recent advances in VLSI technology, the need for efficient real time signal processing units have increased. The multiplier-and-accumulator (MAC) unit is the essential element of the digital signal processor. The aim is to design an 32-bit MAC unit that can perform multiplication and accumulation operation. Hence designing an effective MAC unit with reduced latency is necessary for better performance. The proposed MAC unit uses Carry-Select adder and Vedic multiplier which offers better speed (1.746 ns) in comparison with MAC unit designed using Ripple carry adder (1.782 ns). Urdhva tiryaghbyam sutra is the base sutra used in Vedic multiplier. The design was implemented in Verilog HDL using Xilinx Vivado tool and synthesis was done using Cadence Genus tool.

Wide word‐length carry‐select adder design using ripple carry and carry look‐ahead method based hybrid 4‐bit carry generator

AbstractThis research aims to fill up the research gap in energy‐efficient transistor‐level wide word‐length carry circuit generator by using ripple carry (RC) and carry look‐ahead (CLA) method‐based hybrid 4‐bit carry generation process for wide word‐length carry‐select adder (CSLA). Compared to the existing 4‐bit CLA architectures, the proposed 4‐bit RC‐CLA method‐based hybrid 4‐bit carry generator showed performance improvement in terms of power and power delay product (PDP). Later, the 4‐bit carry architectures (existing and proposed) were used as a base to implement 16‐bit carry select adder (CSA) in order to investigate and compare the effect of using the proposed hybrid RC‐CLA based 4‐bit carry generator in large structures. Unlike 4‐bit operation, the proposed design displayed the best performance in power and PDP for 16‐bit CSA extension, which proves its effectiveness in wide word‐length adder structures.

Performance Analysis of 8-Bit Carry Select Adder

In this study, we evaluated the performance of an 8-bit carry-select adder (CSA) implemented through transmission gates for various metrics such as speed and area. Adders are an important part of digital computer systems and are used to perform additional operations. CSA is a well-known adder type known for its fast performance. Our results suggest that CSA implemented using transmission gates may improve the performance of digital circuits by achieving faster performance due to the low resistance and fast switching properties of these gates. In addition, we also analyzed the area utilization of CSA by measuring the number of transistors in the synthesized design. The integration of transmission gates into the CSA can affect area characteristics and our analysis provides insight into the design's area efficiency. CSA was developed in this study using transmission gate technology along with MTCMOS D-latch to achieve superior performance compared to previous studies. Simulations were performed using 250nm CMOS technology from Tanner and Mentor Graphics. His CSA implementation with transmission gate logic significantly reduced transistor count by 58.85% compared to his conventional CSA. This approach was chosen for its better results and improved overall performance.

Area, Delay, and Energy-Efficient Full Dadda Multiplier

The Dadda algorithm is a parallel structured multiplier, which is quite faster as compared to array multipliers, i.e., Booth, Braun, Baugh-Wooley, etc. However, it consumes more power and needs a larger number of gates for hardware implementation. In this paper, a modified-Dadda algorithm-based multiplier is designed using a proposed half-adder-based carry-select adder with a binary to excess-1 converter and an improved ripple-carry adder (RCA). The proposed design is simulated in different technologies, i.e., Taiwan Semiconductor Manufacturing Company (TSMC) 50[Formula: see text]nm, 90[Formula: see text]nm, and 120[Formula: see text]nm, and on different GHz frequencies, i.e., 0.5, 1, 2, and 3.33[Formula: see text]GHz. Specifically, the 4-bit circuit of the proposed design in TSMC’s 50[Formula: see text]nm technology consumes 25[Formula: see text]uW of power at 3.33[Formula: see text]GHz with 76[Formula: see text]ps of delay. The simulation results reveal that the design is faster, more power-energy-efficient, and requires a smaller number of transistors for implementation as compared to some closely related works. The proposed design can be a promising candidate for low-power and low-cost digital controllers. In the end, the design has been compared with recent relevant works in the literature.

Design of 2-1 Multiplexer based high-speed, Two-Stage 90 nm Carry Select Adder for fast arithmetic units

This paper proposes a new Two-Stage Carry Select Adder (TSCSA) using a single type of leaf cell i.e., a 2-1 Multiplexer. All the existing Carry Select Adders (CaSeAs) are constructed with three stages. The first stage produces the result with input carry ‘0’, the second stage generates an excess-1 result and the third stage is used to select one of the results using multiplexers. The proposed 4-, 8-, 16-, 32-, and 64-bit TSCSA are distinctly designed in two stages only. The carry propagation through adders and full adders is completely eliminated which is the main bottleneck problem for high-speed arithmetic units. A 64-bit TSCSA is distinctly decomposed for maintaining excellent cell regularity that uses one type of cell i.e., 2-1multiplexer. Ripple carry adder blocks in existing designs are replaced with half adders by eliminating the carry propagation. At the outset, the speed of TSCSA is improved by overcoming carry propagation through adder blocks, especially in higher-order adders. The area is the major concern for CaSeAs; is also reduced for TSCSA by maintaining cell regularity. Verilog HDL is used in the design of the TSCSA and existing CaSeAs. Using Cadence NCLaunch, all of the designs are functionally tested. At the 90 nm technology node, all of the designs are generated and executed using Cadence Genus and Innovus, respectively. In comparison to current designs, there is marginal improvement in area and power but there is substantial improvement in speed. The proposed 64-bit TSCSA final ASIC architecture is 9% more compact and dissipates 13% less power. According to the comparison and result analysis, TSCSAs have 69% superior speed than existing designs. As a result, TSCSA works best in low-power, small-area, and fast applications.

Performance Analysis of Notch Filter in ECG Signal Noise Reduction

An electrocardiogram (ECG) is a medical test that records the normal and abnormal condition of the heart. It is an essential tool for identifying vari- ous cardiac related issues. However, ECG wave are often distorted by diverse noise sources, such as movement artifacts or electrical interference. To remove these artifacts and enhance the quality of the ECG signal, various filters are commonly used. The choice of filter type depends on the definite necessities of the application. FIR filters are used in the area that needs linear time response and accurate amplitude response. They have a stable and predictable response and are more robust to coefficient quantization errors. However, they require a larger number of coefficients to achieve the desired frequency response, which can lead to increased computational complexity. The use of digital filters, specifically notch filters, for denoising ECG signals is an effective technique. Adders are essential components in the design of notch filters, and researchers have been exploring different types of adders to improve the parameters of these filters. In this paper, the Ripple carry adder, Carry select Adder, and adder using Carry skip are compared in terms of their performance parame- ters, including area, delay, and power consumption. The RCA is a basic adder, while the C-Skip and C-Select adder are designed to reduce the delay of the addition operation. The results of the study showed that the C-Skip and C- Select adder outperformed the R-Carry adder in terms of delay and power con- sumption. The C-select adder had the lowest delay, while the C-Skip adder had the lowest power consumption. However, the area of the C-select Adder was larger compared to the other adders. Overall, the selection of adder depends on the particular need of the application. Notch filter used for ECG noise removal designed using these adders and its performance is analyzed.

Design of FIR Filter Using Low-Power and High-Speed Carry Select Adder for Low-Power DSP Applications

Adders are one of the basic arithmetic circuits of any processor, microcomputer, multiplication circuits, etc. Presently, the most substantial areas in the research of VLSI design are area, power, and efficient high-speed circuits. In this paper two new architectures Carry Select Adder (CSLA) using D-latch and CSLA using multiplexers are proposed to reduce the power, delay, and its efficiency is compared with conventional carry select adder (CSLA) and existing literature. Architectural level power reduction is the most important area where it plays a vital role in improving the speed and power of the overall circuit. The existing and proposed CSLAs are synthesized with the Synopsys EDA tool using 32 nm technology node is used for the design and implementation. The values obtained across technology in nm underline the dominance of the proposed adder architectures in terms of delay and energy and area efficiency. For the proposed architectures, the evaluation results show that 60%–75% improvement in delay and 22%–56%in power when compared to other architectures. Proposed architectures shows increment in area but overall are delay product reduces compares to existing designs The proposed CSLA-DLATCH-FIR obtained significant reduction for 16-bits for power (46.4 (µW)), delay (0.66), ADP (359.8 × 10–15), and PDP (30.63 × 10–15). While the proposed CSLA-MUX-FIR has attained substantial performance for power (52.44 (µW)), delay (0.82 ns), ADP (457.392 × 10–15), and PDP (42.9 × 10–15). With the use of this proposed CSLA, a FIR filter was able to significantly reduce its power and delay.

A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

This paper proposes a novel architecture of excess-1 adder-based Carry Select Adder (M2CSA) using single leaf cell i.e., 2–1 Multiplexer. M2CSA is designed using a new type of Excess-1 block. The Excess-1 block is designed in a distinct way using 2–1 multiplexers. The architectures of the proposed carry select adder and its internal excess-1 blocks are completely distinct when compared to existing carry select adders. The proposed 4-, 8-, 16-, 32-, and 64-bit M2CSAs use a 2–1 multiplexer only. The complex gates such as XOR gates are eliminated which exist in existing Carry Select Adders (CaSeAs). A 64-bit M2CSA that utilises one kind of 2-1 Mux cell is clearly decomposed to retain outstanding cell regularity. In previous designs, ripple carry adder blocks are substituted with half adders by limiting carry propagation to a particular degree. By avoiding carry propagation over adder blocks, particularly in 32- and 64-bit adders, the performance of M2CSA is initially increased. For CaSeAs, the area is of primary significance; for M2CSAs, it is also diminished by preserving cell regularity. Verilog HDL is utilised in the design of the M2CSA and current CaSeAs. Using Cadence NCLaunch, all of the designs are functionally tested. At a 90nm technology node, all of the designs are generated and executed using Genus and Innovus tools, respectively. As a comparison to prior designs, the 64-bit M2CSA final ASIC architecture is on average 17% less in terms of space. The comparison and result analysis show that 64-bit M2CSA performs 20% and 19% faster than 64-bit SQCSC in terms of performance and power dissipation, respectively.. The proposed 4-, 8-, 16-, 32-, 64- bit M2CSA exhibits less PDP (Power-Delay Product) ranging from 25%–30% concerning SQCSCs. Similarly, EDP (Energy- Delay Product) values for all the designs are calculated. The improvement in EDP for the 4-, 8-, 16-, 32-, 64- bit M2CSA is 41, 38, 42, 43, and 45 percentages compared to 4-, 8-, 16-, 32-, 64- bit SQCSC respectively. Therefore, the M2CSAs outperform the existing designs in terms of EDP by 38%–45%.

A low-cost in-tire-pressure monitoring SoC using integer/floating-point type convolutional neural network inference engine

Tire pressure state is crucial for driving performance and fuel efficiency and is the welfare of the driver. Tire inflation pressure greatly affects fuel consumption, driving dynamics and the tire lifespan. Hence, the state of tire pressure must be continuously sensed for comfort riding, optimal vehicle handling, and safety, and it is necessary for all types of transport. The existing detection methods are high cost and without any redundancy, if the sensor gets fails, which retard its wide application. The support vector machine (SVM) learning method is introduced for tire pressure loss detection. But, this method is not so accurate in detecting the normal and pressure loss judgement of tires. This research presents a novel approach for a tire pressure monitoring system (TPMS) to reduce the cost of sensor-based frames. The proposed model comes under three stages: pre-processing, feature extraction and tier pressure detection. Initially, an adaptive and unbiased Kalman filter (KF) with a recursive least square (RLS) algorithm (AUK-RLS) approach is introduced to eliminate manufacturing errors in speed gear. The second stage is the extraction of features. Statistical, frequency domain, and fitted frequency domain characteristics features are extracted from the wheel speed signal in this stage. It is fed to the deep learning (DL) model to perform the judgement of tier state. While using floating point model for the operation and storage process, the hardware cost of the DL model tends to be high. To tackle this issue, the convolutional neural network (CNN) hardware design will be optimized by combining both Integer/Floating-Point type inference engines. The design modules of the CNN interference engine are insisted of buffers, on-chip/off-chip memories, controllers, fine state machine (FSM), processing engine (PE) and routers. The PE module needs several adders and multiplier units, and this performs the convolution operation. Therefore, to diminish the area, delay and power consumption, the modified adder and multiplier design named Vedic multiplier based Carry select adder with simplified combinational logics (CSLA-SCL) is emphasized. The proposed system is implemented using Verilog code synthesis in the Xilinx ISE 14.5 simulator platform. The performance measure of pressure loss detection in terms of accuracy (99.25%) and errors are examined. Also, the performance measure of the detection model with the proposed adder and multiplier design is examined in terms of area utilization, power (145 mW), frequency (756 MHz) and delay (7.12 ns).

IMPLY-Based High-Speed Conditional Carry and Carry Select Adders for In-Memory Computing

Big data applications involved with neural networks requires frequent data transfer between memory and processing elements and thus, take a significant portion of energy. One possible method is to realize logic operations inside the memory, often known as <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in-memory computing</i> . The memristor employed in a crossbar can also conduct logic operations, making it a promising candidate for enabling such designs. In-memory computing can vastly improve speed efficiency by significantly reducing memory access time and energy. Therefore, efficient operations inside the memory are crucial for data-intensive applications. This paper presents two high-speed adders in memristive technology, which are derived using IMPLY-based logic operations and can be implemented on a crossbar architecture for in-memory computing. One is a carry select adder, which uses efficient ripple carry adders and multiplexers. While the other is a conditional carry adder, designed using a modified half adder and multiplexers. An IMPLY-based multiplexer and modified half adder are proposed as part of these adders. A modified half adder calculates the sum of two inputs and two carry outputs for various carry inputs. Compared to conventional adder designs, the speed of these two adders has been significantly enhanced. In particular, the proposed 32-bit Carry Select Adder and Conditional Carry Adder take 123 and 90 computational steps, respectively. The proposed adders have improved the speed by 30 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\%$</tex-math></inline-formula> and 49 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\%$</tex-math></inline-formula> , respectively, compared to the best-existing adder in IMPLY. Further, this paper presents computational steps and the number of memristors required for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$n$</tex-math></inline-formula> -bit adders. The proposed circuits were simulated using the VTEAM model, and energy consumed per each adder is calculated from the simulations.

Performance Measurement of Energy Efficient and Highly Scalable Hybrid Adder

The adders are the vital arithmetic operation for any arithmetic operations like multiplication, subtraction, and division. Binary number additions are performed by the digital circuit known as the adder. In VLSI (Very Large Scale Integration), the full adder is a basic component as it plays a major role in designing the integrated circuits applications. To minimize the power, various adder designs are implemented and each implemented designs undergo defined drawbacks. The designed adder requires high power when the driving capability is perfect and requires low power when the delay occurred is more. To overcome such issues and to obtain better performance, a novel parallel adder is proposed. The design of adder is initiated with 1 bit and has been extended up to 32 bits so as verify its scalability. This proposed novel parallel adder is attained from the carry look-ahead adder. The merits of this suggested adder are better speed, power consumption and delay, and the capability in driving. Thus designed adders are verified for different supply, delay, power, leakage and its performance is found to be superior to competitive Manchester Carry Chain Adder (MCCA), Carry Look Ahead Adder (CLAA), Carry Select Adder (CSLA), Carry Select Adder (CSA) and other adders.

HIGH-EFFICIENT VLSI ARCHITECTURE FOR THREE OPERAND BINARY ADDER

This paper presents a VLSI architecture for a three-operand binary adder. The proposed design is based on a carry-select adder (CSLA) and Han-Carlson (HCA) adder. Carry-select adder is known for its high speed and low power consumption. The architecture uses a novel carry-in selection scheme that reduces the number of logic gates required for carry generation. Additionally, Han-Carlson (HCA), a parallel prefix two-operand adder, can also be used for three-operand addition, significantly reducing the critical path delay at the cost of supplementary hardware. In addition to perform the three-operand binary addition with significantly less space and low power consumption, a novel high-speed and area-efficient adder architecture is suggested. This architecture uses pre-compute bitwise addition followed by carry-selection computation logic. The design also includes a parallel processing unit that allows the efficient computation for multiple operands of multiple results simultaneously. The proposed architecture has been implemented in Verilog HDL and synthesized using a 32nm CMOS technology. The simulation results show that the design achieves high performance with low power consumption. Additionally, the proposed design can be easily scaled to handle larger operands without sacrificing performance or area overhead. When compared to the current three-operand adder approaches, the suggested adder achieves the lowest ADP and PDP.

Physical Design of 64-bit Multiplier and Accumulator (MAC) Unit Using Vedic Multiplier and CLA Adder

In digital signal processing, communication systems and many other applications, multiplier and accumulator units play a crucial role. This work presents an overview of 64-bit MAC Unit, where Vedic multiplier is used as multiplier unit and compared Carry select adders (CSA) and Carry look-ahead adder (CLA) which must be used for adder unit, accumulator unit consist of Parallel in parallel out (PIPO) shift registers. As a result, CLA adder to be more effective in terms of lower delay by comparing with other adders. The MAC Unit was modelled using Verilog-HDL, where its functional verification and synthesized was done using Intel Quartus Prime 21.1, which was simulated on Questa Intel FPGA 21.1. Further GDSII file was created using the cadence tool with the help of Incisive for functional simulation, Genus for synthesis and pre-layout timing analysis, and innovus for physical design. Entire study was carried out in 180nm technology from RTL-GDSII. The delay, power, area was monitored, the memory usage, Pre-Clock Tree Synthesis, Post-Clock Tree Synthesis (CTS) were noted before and after optimization of design.

FPGA design of arithmetic optimised APT-VDF using reusable Vedic multiplier with simplified combinational logics for medical signal denoising

ABSTRACT All-pass transformation (APT)-based variable digital filters (VDFs) can be used in different biomedical signal-processing applications, particularly in electrocardiograph denoising. In this paper, arithmetic optimised APT-VDF is proposed by modifying the hardware structure of APT-VDF based on arithmetic perception to enhance the performance in terms of area, speed and power consumption. The core blocks of the suggested Arithmetic Optimised APT-VDF (AOAPT-VDF)are adders and multipliers. This paper introduces a new reusable Vedic multiplier with redundant detection unit to identify redundant computations while generating the partial products. Also, a new Carry select adder (CSLA) with simplified combinational logics is proposed to improve the performance of the CSLA by simplifying the partial sum and carry generation logics without requiring Ripple Carry Adders. The proposed Reusable Vedic Multiplier with Redundant Detection Logic (RVM-RDL) also reuses the same vertical and cross-product generation units repetitively to reduce the area while increasing the bit length. The effectiveness of the suggested AOAPT is analysed utilising the MIT-BIH Arrhythmia Database. The proposed AOAPT-VDF consumes only 0.21 W power and achieves a 235.50 MHz operating frequency.