Implementation of Area Efficient Carry Select Adder using Binary to Excess1 Code

Abstract

Adders are widely used as essential parts in the design of digital integrated circuits. The Carry Select Adder (CSA) is unique among conventional adder topologies in that it operates quickly. There is a need for speedier arithmetic units as well as ones that use less power and take up less space as the mobile sector grows quickly. The Carry-Select method for adder design with carry propagation achieves a good trade-off between performance and cost. However, because it uses two ripple carry adders (RCA), the traditional CSA design still has a significant area overhead. A Binary to Excess-1 code converter (BE-1 converter) has been used in the development of a modified CSA design to overcome the issue. This study presents a practical method for reducing the size and power footprint of the CSA by introducing gate-level changes to the BE-1 converter design. Making use of this alteration, a 4-bit CSA architecture with a BE-1 converter is developed and contrasted with the industry standard CSA design. These designs are evaluated considering their area and power characteristics. The analytical results show that the suggested CSA structure is better than the traditional one and that using a CSA with a BE-1 converter is an efficient way to create a VLSI design.