Design of area and delay efficient Vedic multiplier using Carry Select Adder

Abstract

In this paper, Vedic multiplier is designed using area-efficient Carry Select Adder (CSLA). As the multiplication is the process of subsequent addition, adder is important block in implementation of multiplier. Digital adder has problem of carry propagation, thus carry select adder is used instead of simple Ripple Carry Adder (RCA). Carry select adder is known to be one of the fastest adder structures. Here Vedic multiplier is implemented instead of normal multipliers like add and shift multiplier, array multiplier etc. The goal of this paper is to design Vedic multiplier based on crosswise and vertical algorithms using area-efficient CSLA. Conventional CSLA designs like Binary to Excess one Converter (BEC) based CSLA and Modified CSLA (MCSLA) are compared with proposed CSLA design to prove its efficiency. It shows improved performance in terms of area. This renovated CSLA is used to design proposed Vedic multiplier. It has 6% less area than Vedic multiplier using MCSLA and 16% less area than Vedic multiplier using BEC-based CSLA. Proposed design is also compared with the Booth multiplier. Proposed multiplier showed more excellent results than Booth multiplier.