Design and analysis of high speed and low area vedic multiplier using carry select adder

Abstract

In the work below we have formulated and examined 8-bit vedic multiplier using (RC)Ripple carry adder, (CSL)Carry select adder, (CSl)Carry select adder using Binary to excess- 1(BEC) converter, Ling Carry select(CS) adder, (BK)Brent Kung, (CSL)Carry Select Adder. The designs were simulated using ModelSim-Altera 6.3g and synthesized using Xilinx ISE Design Suite 12.1. The speed and area of the (VM)vedic multiplier with different carry select adder architectures are compared. It is found that the 8-bit (VM)vedic multiplier using (BK)Brent Kung (CSL)Carry select adder had turned out to produce eminent results in terms of area and delay.