Carry Select Adder Research Articles

Self-Repairing Hybrid Adder With Hot-Standby Topology Using Fault-Localization

Effective self-repairing can be achieved if the fault along with its exact location can be determined. In this paper, a self-repairing hybrid adder is proposed with fault localization. It uses the advantages of ripple carry adder and carry-select adder to reduce the delay and area overhead. The proposed adder reduces the transistor count by 115% to 76.76% as compared to the existing self-checking carry-select adders. Moreover, the proposed design can detect and localize multiple faults. The fault-recovery is achieved by using the hot-standby approach in which the faulty module is replaced by a functioning module at run-time. In case of 3 consecutive faults, the probability of fault recovery has been found to be 96.1% for a 64-bit adder with 8 blocks, where each block has 9 full adders.

Design and Implementation of 256 Bit Modified Square Root Carry Select Adder for Area and Delay Reduction

This paper models the behaviour of modified Square Root Carry Select Adder and goes deep to investigate on its scope of reducing area and delay. This helps to overcome the drawback of conventional RCA by performing operations simultaneously for both Cin = 0 and Cin = 1, and the output is multiplexed to obtain the desired response. The work explores opportunities to reduce the area with introduction of BEC logic instead of second block RCA. The implementation of a 4 bit MCSLA and its capability of extending its word size to 8, 16, 32, 64, 128 and 256 bits are presented. The experimental result helps to verify the effectiveness of the approach. This provides understanding on how the reduction of area can bring vital improvements in Very Large Scale Integration.

Updated Efficient Area -Carry Select Adder for Low Complexity D LATCH Configuration by disease identification in brain tumor hyper spectral image

Objective: In this research work presents an efficient way Carry Select Adder (CSLA) performance and estimation. The CSLA is utilized in several system to mitigate the issue of carry propagation delay that is happens by severally generating various carries and to get the sum, select a carry because of the uses of various pairs of RCA to provide the sum of the partial section also carry by consisting carry input but the CSLA isn't time economical, then by the multiplexers extreme total and carry is chosen in the selected section. Methodology: The fundamental plan of this work is to attain maximum speed and minimum power consumption by using Binary to Excess-1. Convertor rather than RCA within the regular CSLA. Here RCA denotes the Ripple Carry Adder section. At the span to more cut back the facility consumption, a method of CSLA with D LATCH is implemented during this research work. The look of Updated Efficient Area -Carry Select Adder (UEA-CSLA) is evaluated and intended in XILINX ISE design suite 14. 5 tools. This VLSI arrangement is utilized in picture preparing application by concluding the cerebrum tumor discovery. Conclusion: In this study, medicinal pictures estimation, investigation districts in the multi phantom picture isn't that much proficient to defeat this disadvantage here utilized hyper spectral picture method is presented a sifting procedure in VLSI innovation restriction of cerebrum tumor is performed Updated Efficient Area - Carry Select Adder propagation result dependent on Matrix Laboratory in the adaptation of R2018b.

Enhanced 32-Bit Adder Implementation using Different Configurations of Adders

Adders play a essential role with in the digital signal process systems. The 32-bit configuration is commonly used in few computerized systems and processors. In this paper, detail study about the implementation of 32-bit adders like Ripple Carry Adder (RCA), Carry Select adder (CSLA) and Carry Increment adder (CINA) is done for various configurational full adders using VHDL. The outcomes are acquired by executing VHDL in Xilinx ISE 14.5 with speed grade -5 of Spartan 3E family device.

RTL Design of Efficient High-Speed Adders using Quantum-Dot Cellular Automatation

This article presents the design of high-speed adders using Quantum cellular automata. Quantum Automata is an efficient evaluation platform than CMOS in nanotechnology. Power, surface and performance play a virtual role in nanotechnology. Quantum Automata is an emerging technology in nanotechnology. QCA provides more speed, less power consumption and large scale integration in VLSI. By using Quantum-Dot cellular automata, we can reduce the power of leaks. Generally, for transferring the data and store data, electric fields are used in CMOS technology but in QCA, storing the data and transfer the data done by electronic polarization. This article presents different combinational logic circuits depend on QCA technology. The proposed modified CSLA (carry select adder) offer the best results of delay compared to the Ripple carry adder (RCA).

Power Optimized Carry Select Adder Using Power Gated ALFA Cell

Power Optimized Carry Select Adder Using Power Gated ALFA Cell

Area and Power Potent VLSI Architecture for Modified CSLA with A Logic Optimization Technique

Through generations, in an endeavor to pioneer innovative circuit designs, an adder is having the greatest importance as it is a basic building block to decide the system’s overall performance. Wide varieties of adders are used for a plethora of applications in the field of Signal Processing and VLSI systems. Most predominantly used Speed efficient architecture for performing n-bit addition in VLSI applications is Square Root Carry Select Adder (SQRT-CSLA) as it pre-computes the carry and sum by assuming input carry as ‘zero’ and ‘one’. But the overall area usage is high as it uses more number of full adders when compared to Ripple Carry Adder. Though, the existing adder designing techniques are area efficient, there is still scope to achieve area efficiency as area decides the cost of the VLSI Systems. Not only area-efficient but also power potent architectures are required to accelerate the overall performance of the VLSI systems. To meet these objectives, this paper proposes an efficient VLSI architecture for carry select adder by using logic optimization technique addressing performance constraints. The proposed architecture is designed and implemented using cadence encounter tool for different data widths ranging from 16 bits to 128 bits. The performance of the proposed 128-bit architecture achieves an area improvement of 63.43% and a power improvement of 71.00923% when compared to 128-bit SQRT-CSLA architecture

Area and power efficient pipelined hybrid merged adders for customized deep learning framework for FPGA implementation

With the rapid growth of deep learning and neural network algorithms, various fields such as communication, Industrial automation, computer vision system and medical applications have seen the drastic improvements in recent years. However, deep learning and neural network models are increasing day by day, while model parameters are used for representing the models. Although the existing models use efficient GPU for accommodating these models, their implementation in the dedicated embedded devices needs more optimization which remains a real challenge for researchers. Thus paper, carries an investigation of deep learning frameworks, more particularly as review of adders implemented in the deep learning framework. A new pipelined hybrid merged adders (PHMAC) optimized for FPGA architecture which has more efficient in terms of area and power is presented. The proposed adders represent the integration of the principle of carry select and carry look ahead principle of adders in which LUT is re-used for the different inputs which consume less power and provide effective area utilization. The proposed adders were investigated on different FPGA architectures in which the power and area were analyzed. Comparison of the proposed adders with the other adders such as carry select adders (CSA), carry look ahead adder (CLA), Carry skip adders and Koggle Stone adders has been made and results have proved to be highly vital into a 50% reduction in the area, power and 45% when compared with above mentioned traditional adders.

An Energy and Area Efficient Carry Select Adder with Dual Carry Adder Cell

In this paper, an energy and area efficient carry select adder (CSLA) is proposed. To minimize the redundant logic operation of a regular CSLA, a dual carry adder cell is proposed. The proposed dual carry adder is composed of an XOR/XNOR cell and two pairs of sum-carry cells. Both CMOS logic and a transmission gate were applied to the dual carry adder cell to achieve fast and energy efficient operation. Eight-bit, 16b, and 32b square-root (SQRT) CSLAs based on the proposed dual carry adder were developed. The post-layout simulation based on a SMIC 55 nm process demonstrated that the proposed CSLAs reduced power consumption by 68.4–72.2% with a slight delay increase for different bit widths. As the dual carry adder had much fewer transistors than the two regular full adders, the area of the proposed CSLAs was reduced by 45.8–51.1%. The area-power-delay product of the proposed CSLA improved 5.1×–6.73× compared with the regular CSLA.

High throughput FIR filter architectures using retiming and modified CSLA based adders

A methodology to improve the throughput of FIR filters through the effective use of retiming and efficient add–multiply operation is presented in this study. Delay, energy and area efficient linear and square root carry-select adder (CSLA) structures are obtained by combining modified forms of carry look-ahead and carry-skip adder concepts to concatenated CSLA modules. The computational speed is enhanced by the quick generation and transmission of the end module carries by the module carry generation blocks. The delay performance of booth multiplier is improved by performing the partial product addition using the proposed square root CSLA. Two versions of the proposed filters are (a) high throughput low power and low complex retimed FIR filter and (b) high throughput energy efficient retimed FIR filter. The critical path delay, power, power–delay product and area–delay product of the proposed filter-2 are reduced by 71, 38, 82 and 78%, respectively, with respect to flexible retimed filter and by 40, 11, 47 and 37%, respectively, with respect to modified transpose form filter for a filter length of 64. Cadence software with gpdk 45 nm standard cell library is used for the design and implementation.

Optimization of CSA for Low Power and High-Speed using MTCMOS and GDI Techniques

The basic operation involved in any analog, digital, control system, DSP’s is addition. Performance and reliability of almost every digital system is depends on performance of adder. Over the decade, many adder architectures are proposed and still research work is going on adder to obtain the best results in power, delay and power delay product (PDP). In this paper we proposed one of the fastest adder architecture called Carry Select adder (CSA) and optimization is done for performance parameters like delay and power using GDI (Gate Diffused Input) and MTCMOS techniques. Implementation has been done in standard gpdk 90nm technology using Cadence tool.

Design of High-Speed Desensitized FIR Filter Employing Reduced Complexity SQRT Carry Select Adder

In this research, a highly efficient desensitized FIR filter is designed to enhance the performance of digital filtering operation. With regard to FIR filter design, Multiplication and Accumulation component (MAC) forms the core processing entity. Half-band filters employing Ripple Carry Adder (RCA) based MAC structures have a sizeable number of logical elements, leading to high delay and high power consumption. To minimize these issues, a modified Booth multiplier encompassing SQRT Carry Select Adder (CSLA) based MAC component is proposed for the desensitized filter with reduced coefficients and employing lesser number of logical elements forgiving optimum performance with respect to delay and power consumption. The suggested FIR filter is simulated and assessed using EDA simulation tools from Modelsim 6.3c and Xilinx ISE. The results obtained from the proposed Desensitized FIR filter employing the modified booth multiplier with reduced complexity based SQRT CSLA show encouraging signs with respect to 12.08% reduction in delay and 2.2% reduction in power consumption when compared with traditional RCA based digital FIR filter.

Design of 32 Tap Finite Impulse Response Filter using Vedic Multiplier and KoggeStone Adder

32 tap FIR Filter is designed utilizing Vedic multiplier and Kogge stone adder. Effective performance is important for FIR Filter design due to increasing complexity. Two basic opertaions of FIR Filter are multiplication and addition. So, for multiplication, vedic multiplier is used and addition is performed by KS adder which is faster than other adders like Ripple carry adder, Look ahead carry adder, Carry select adder etc. K S adder is used to overcome problem of carry propagation. The objective is to minimize the propagation delay i.e increasing the speed of filter. Synthesis & simulation is done by Xilinx ISE 14.7 software tool using VHDL.

High throughput K best MIMO detector using modified final selector based carry select adder

The VLSI architecture of novel K best detector using Carry Select Adder (CSA) with Modified Final Selector Unit (MFSU) is proposed for wireless communication applications. The challenge in K best detector design is to utilize less number of levels with high throughput. To overcome this limitation, pipelining technique is exploited in expansion and minimization block. This architecture also includes the sorter block which provides these signals in a proper format and then the processing element processed the signals from the sorter block and determines the best signal. This proposed design can achieve high throughput with the clock frequency as 311.6 MHz. The proposed K best detector is synthesized and simulated using Xilinx ISE and it is coded in Verilog HDL. When compared to ISCAS’13, DATE’11, KB-HPED, KB-VPED, K best detector with CSA, the proposed novel K best detector with MFSU based CSA reduces the number of slices by 11.89%, 9.85%, 8.29%, 6.12%, 3.56% and reduces the number of 4 input LUTs by 9.38%, 0.1%, 8.10%, 3.15%, 1.9% respectively. The proposed technique reduces the energy consumption by 33.33%, 16.5% and 5.18% compared to KB-HPED, KB-VPED and KB with CSA.

Concurrent Error Detectable Carry Select Adder with Easy Testability

A concurrent error detectable adder with easy testability is proposed. The proposed adder is based on a multi-block carry select adder. Any erroneous output of the adder caused by a fault modeled as a single stuck-at fault can be detected by comparing the predicted parity of the sum with the parity of the sum, i.e., the XORed value of the sum bits, and comparing the duplicated carry outputs. The adder is also testable with only 10 input patterns under single stuck-at fault model. This property eases detection of a fault before the occurrence of a second fault. Both the concurrent error detectability to detect erroneous results and the easy testability to find a fault during operation are important for realizing reliable systems. Both the concurrent error detectability and the easy testability of the proposed adder are proven. A 32-bit adder has been designed. Its hardware overhead is about 70 percent. Its concurrent error detectability and 100 percent test coverage through the 10 patterns has been confirmed by fault simulation.

Speed and energy optimized quasi-delay-insensitive block carry lookahead adder.

We present a new asynchronous quasi-delay-insensitive (QDI) block carry lookahead adder with redundant carry (BCLARC) realized using delay-insensitive dual-rail data encoding and 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The proposed QDI BCLARC is found to be faster and energy-efficient than the existing asynchronous adders which are QDI and non-QDI (i.e., relative-timed). Compared to existing asynchronous adders corresponding to various architectures such as the ripple carry adder (RCA), the conventional carry lookahead adder (CCLA), the carry select adder (CSLA), the BCLARC, and the hybrid BCLARC-RCA, the proposed BCLARC is found to be faster and more energy-optimized. The cycle time (CT), which is expressed as the sum of the worst-case times taken for processing the data and the spacer, governs the speed. The product of average power dissipation and CT viz. the power-cycle time product (PCTP) defines the low power/energy efficiency. For a 32-bit addition, the proposed QDI BCLARC achieves the following reductions in design metrics on average over its counterparts when considering RTZ and RTO handshaking: i) 20.5% and 19.6% reductions in CT and PCTP respectively compared to an optimum QDI early output RCA, ii) 16.5% and 15.8% reductions in CT and PCTP respectively compared to an optimum relative-timed RCA, iii) 32.9% and 35.9% reductions in CT and PCTP respectively compared to an optimum uniform input-partitioned QDI early output CSLA, iv) 47.5% and 47.2% reductions in CT and PCTP respectively compared to an optimum QDI early output CCLA, v) 14.2% and 27.3% reductions in CT and PCTP respectively compared to an optimum QDI early output BCLARC, and vi) 12.2% and 11.6% reductions in CT and PCTP respectively compared to an optimum QDI early output hybrid BCLARC-RCA. The adders were implemented using a 32/28nm CMOS technology.

The recursive multiplexer based multipliers

ABSTRACT For high speed multiplier implementation, the recursive architecture is a parallel and modular approach with low complexity. However, compared to the conventional array multiplier, it costs more area due to the interconnection between sub-modules. In this study, the multiplexer based multiplier is adopted as the lower-level multiplier in the recursive architecture because it outperforms the conventional array multiplier in terms of speed, area, and power consumption. To further improve the speed performance, the proposed hybrid architecture exploits the carry-select adders (CSL) for partial products accumulation. The design is synthesized using TSMC 0.18μm standard cell process. According to the experimental results, the propagation delay is reduced by 20.5% and 40.9% respectively, compared to the optimized mux-multiplier and the conventional array multiplier. In addition, we reduce the proposed architecture to a partially truncated circuit for error tolerant applications. Without affecting the speed, both the power consumption and circuit area are further reduced by 25% approximately.

Performance Analysis of FIR Filter Design Using Vedic Multiplier with SQRT based Carry Select Adder

Performance Analysis of FIR Filter Design Using Vedic Multiplier with SQRT based Carry Select Adder

A Low-Power VLSI Implementation of RFIR Filter Design using Radix-2 Algorithm with LCSLA

ABSTRACT The multimedia applications and mobile communication systems require an efficient reconfigurable finite impulse response (RFIR) filter designs for achieving low area, power, cost, and high speed of system operation. In this paper, an efficient RFIR filter is designed based on the Radix-2 algorithm and Look-up-table Carry Select Adder (Radix 2 – LCSLA). Generally, the RFIR filter is controlled by multiplier and adder, which improves the performances of the filter. Hence, this research work is mostly concentrated on the multiplier and adder design. Here, the radix-2 algorithm is used instead of normal multiplier for multiplication operation in the RFIR filter design. Additionally, CSLA and LCSLA approaches used in the Radix-2 structure for adding partial products. The LCSLA has achieved better performance compared to the normal CSLA approaches. In this paper, both the Radix-2 algorithm and LCSLA approach improved the performances of the proposed RFIR filter design. The proposed RFIR filter design was implemented in the Xilinx and Cadence RTL compiler by using the Verilog code. The RFIR-Radix 2-LCSLA filter design was verified in the Modelsim by utilizing the Verilog code. The experimental result showed that the RFIR-Radix 2-LCSLA methodology has improved the performance of ASIC and FPGA in the RFIR filter design up to 5–15% compared to the existing filter architecture: DA-RFIR and LC-CBA-RFIR methods.

Adaptive absolute SCORE algorithm for spectrum sensing in cognitive radio

The Cognitive Radio (CR) is one of the significant technology to enhance the spectrum utilization efficiency. The Radio Frequency (RF) spectrum is the most valuable natural resource. Due to an increased usage of the cognitive radio, the sensing issues in spectrum are increasing day by day. The CR is emerging technologies that increase the effectiveness and efficiency of the spread spectrum communication. Generally, the spectrum sensing is based on the energy detection and cyclostationary feature detection. The energy detection is a fundamental basic spectrum sensing technique. However, it performs poorly under a low Signal-to-Noise Ratio (SNR) environment. The cyclostationary based sensing technique improves Primary Users (PUs) detection performance with the high complexity of implementation and hardware utilization. Traditional median and Finite Impulse Response (FIR) filters are utilized complex adder and multiplier, which requires large memory space to store the filter coefficients and more hardware utilization. Hence, these filters have computational complexity and more hardware utilization. To overcome above-mentioned problems, Adaptive Absolute SCORE (AA-SCORE) architecture is designed based on optimal FIR filter for further reducing the system complexity to enhance the spectrum utilization efficiency in CR. In this research, the FIR filter is designed by using Radix-8 and Carry Select Adder (CSLA) for reducing the filter complexity. The proposed method is named as AAS-R8-CSLA architecture. The AAS-R8-CSLA architecture was implemented in the Field Programmable Gate Array (FPGA) platform through Verilog code. In order to improve the spectrum utilization efficiency of CR by using AAS-R8-CSLA. The experimental outcome showed that the proposed AAS-R8-CSLA architecture has improved FPGA performance up to 2–3% compared to existing methods like AAS and ACS architecture.