Self-Repairing Hybrid Adder With Hot-Standby Topology Using Fault-Localization

Muhammad Ali Akbar,Bo Wang,Amine Bermak

doi:10.1109/access.2020.3016427

Muhammad Ali Akbar, Bo Wang + Show 1 more

Open Access

https://doi.org/10.1109/access.2020.3016427

Copy DOI

Abstract

Effective self-repairing can be achieved if the fault along with its exact location can be determined. In this paper, a self-repairing hybrid adder is proposed with fault localization. It uses the advantages of ripple carry adder and carry-select adder to reduce the delay and area overhead. The proposed adder reduces the transistor count by 115% to 76.76% as compared to the existing self-checking carry-select adders. Moreover, the proposed design can detect and localize multiple faults. The fault-recovery is achieved by using the hot-standby approach in which the faulty module is replaced by a functioning module at run-time. In case of 3 consecutive faults, the probability of fault recovery has been found to be 96.1% for a 64-bit adder with 8 blocks, where each block has 9 full adders.

Highlights

T HE possibility of single-event-upset (SEU) in digital systems has risen as a result of the increase of onchip system complexity as well as reduced clock cycles [1], [2]
The transistor counts of each module for self-checking and self-repairing hybrid adder (HA) is presented in Table
It should be noted that the Sum and Carry bypass modules are required for selfrepairing design, they are not considered while comparing the area-overhead of self-checking design

Summary

INTRODUCTION

T HE possibility of single-event-upset (SEU) in digital systems has risen as a result of the increase of onchip system complexity as well as reduced clock cycles [1], [2]. One of such techniques is the selfrepairing signed digit adder proposed in [18], in which fault localization is achieved because of the limited propagation of carry chains to the neighboring adder block It uses both hardware and time redundancy for self-checking and selfrepair. In [11], a selfchecking full adder was presented which can detect a fault based on its internal functionality and is independent of the Since the goal of this design is to reduce the area overhead without compromising the reliability, Equations Eq (1) to (3) which are used for designing a self-checking and fault localized full-adder need to be implemented with minimum transistor count.

SELF-REPAIRING APPROACH

RESULTS AND BENCHMARK

COMPARISON WITH SELF-REPAIRING APPROACHES

CONCLUSION