Design of Proficient Two Operand Adder Using Hybrid Carry Select Adder with FPGA Implementation

Abstract

In every modern ICs the adders are essential components. Adder’s performance has a substantial impact on the architecture of signal processing, controller, the module of filter, the module of data storage, etc., high-speed and area-efficient circuits are the most substantial parameters in every modern integrated circuit. Carry select adder operates at high speed, but it consumes more power due to the large area. The present approach discloses different VLSI hybrid carry select adder architectures. The hybrid technology-based Carry Select adder (CSELA) consists of two stages, namely the Hancarlson adder stage and Hybrid Stage is proposed. In this technique, all the stages (4 bits in each stage) are performed simultaneously to improve the speed and area further. The propagation delays of the proposed adder are the summation of two full adders, seven Multiplexers (4:1) and BEC(3 bit) for producing Cout. The proposed work indicates that the hybrid carry select adder operates at high a speed with a lesser area than the conventional adder. The proposed design is simulated and synthesized in Xilinx ISE 12.1 using Verilog HDL with a family of Vertex6 FPGA devices (Device No. XC6VLX75T, Package FF484, Speed -3). The synthesized report shows that the speed of the proposed adder is improved by 49.06%, 52.61%, 47.58%, 19.08%, 39.9%, 1.25%, 44.43%,19.08%, 44.07% and 71.59% compared to RCA, CBL-based CSELA, CLA, Weinberger BEC-based CSELA,D latched CSELA, Brent Kung CSELA, Brent Kung RCA-based CSELA, CSA Weinberger, Conventional CSELA and Ling CSELA, respectively.