Design of carry select adder for low-power and high speed VLSI applications

Abstract

Low-power and high-performance VLSI systems are increasingly used in portable and mobile devices, multi-standard wireless receivers, and in biomedical applications. An adder is main component of an arithmetic unit. An efficient adder design essentially improves the performance of a complex DSP system. Carry select adder (CSLA) is known to be the fastest adder among the conventional adder structures. This work presents a method to eliminate all the unnecessary logic operations present in conventional CSLA and suggest a new logic formulation for CSLA. In the suggested scheme, the selection of carry (CS) is performed before the calculation of final sum, which different from the conventional CSLA. The proposed CSLA was synthesized using Xilinx ISE and power was analyzed using Xilinx Xpower Analyzer.