Design of 2-1 Multiplexer based high-speed, Two-Stage 90 nm Carry Select Adder for fast arithmetic units

Abstract

This paper proposes a new Two-Stage Carry Select Adder (TSCSA) using a single type of leaf cell i.e., a 2-1 Multiplexer. All the existing Carry Select Adders (CaSeAs) are constructed with three stages. The first stage produces the result with input carry ‘0’, the second stage generates an excess-1 result and the third stage is used to select one of the results using multiplexers. The proposed 4-, 8-, 16-, 32-, and 64-bit TSCSA are distinctly designed in two stages only. The carry propagation through adders and full adders is completely eliminated which is the main bottleneck problem for high-speed arithmetic units. A 64-bit TSCSA is distinctly decomposed for maintaining excellent cell regularity that uses one type of cell i.e., 2-1multiplexer. Ripple carry adder blocks in existing designs are replaced with half adders by eliminating the carry propagation. At the outset, the speed of TSCSA is improved by overcoming carry propagation through adder blocks, especially in higher-order adders. The area is the major concern for CaSeAs; is also reduced for TSCSA by maintaining cell regularity. Verilog HDL is used in the design of the TSCSA and existing CaSeAs. Using Cadence NCLaunch, all of the designs are functionally tested. At the 90 nm technology node, all of the designs are generated and executed using Cadence Genus and Innovus, respectively. In comparison to current designs, there is marginal improvement in area and power but there is substantial improvement in speed. The proposed 64-bit TSCSA final ASIC architecture is 9% more compact and dissipates 13% less power. According to the comparison and result analysis, TSCSAs have 69% superior speed than existing designs. As a result, TSCSA works best in low-power, small-area, and fast applications.