—This paper proposes a differential 10-bit 1 MS/s successive approximation register (SAR) analog to digital converter (ADC) with input range (IR) extension. Employing 512 capacitor units and a reference voltage VREF, it attains a ±1.875VREF input range and a resolution of 10.91 bits. The hybrid SAR ADC decomposes the capacitive digital-to-analog converter (CDAC) into an incremental CDAC and a binary-weighted CDAC. For input signals larger than 0.75 VREF, the incremental CDAC is used to reduce the net sampling charge by biasing its capacitor bottom plates on proper reference voltage to implement input range extension. Furthermore, the increment CDAC contributes to enhancing linearity. The input frequency limitation is theoretically analyzed in the paper. This design is implemented with a 180-nm CMOS technology and achieves a 10.47 effective number of bits (ENOB). It consumes 26.8 μW at 1 MS/s with a 1.8-V supply and occupies an area of 0.0118 mm2.