Capacitive DAC Research Articles

A 12-bit compact column-parallel SAR ADC with dynamic power control technique for high-speed CMOS image sensors

This paper presents a 12-bit column-parallel successive approximation register analog-to-digital converter (SAR ADC) for high-speed CMOS image sensors. A segmented binary-weighted switched capacitor digital-to-analog converter (CDAC) and a staggered structure MOM unit capacitor is used to reduce the ADC area and to make its layout fit double pixel pitches. An electrical field shielding layout method is proposed to eliminate the parasitic capacitance on the top plate of the unit capacitor. A dynamic power control technique is proposed to reduce the power consumption of a single channel during readout. An off-chip foreground digital calibration is adopted to compensate for the nonlinearity due to the mismatch of unit capacitors among the CDAC. The prototype SAR ADC is fabricated in a 0.18 μm 1P5M CIS process. A single SAR ADC occupies 20 × 2020 μm2. Sampling at 833 kS/s, the measured differential nonlinearity, integral nonlinearity and effective number of bits of SAR ADC with calibration are 0.9/−1 LSB, 1/−1.1 LSB and 11.24 bits, respectively; the power consumption is only 0.26 mW under a 1.8-V supply and decreases linearly as the frame rate decreases.

A 5.8 nW 9.1-ENOB 1-kS/s Local Asynchronous Successive Approximation Register ADC for Implantable Medical Device

This brief presents a 10-bits successive approximation register analog-to-digital converter (ADC) with a sampling rate of 1 kS/s for implantable medical devices. This ADC is implemented in a 65-nm CMOS process in which leakage current will be a key design parameter. It imposes the highest degree of simplicity in the design of the ADCs architecture. Thus, the transistor count is minimized, which reduces not only the active power, but also the number of leakage sources. The modified top-plate V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cm</sub> -based switching offers energy efficient switching at the capacitive-DAC (CDAC) and uses simple control logic. In addition, the proposed asymmetrical metal-oxide-metal capacitor reduces the size of the CDAC by 90% for a given gain error. Furthermore, the input referred offset voltage of the dynamic comparator can be improved by the top-plate V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cm</sub> -based switching method at system level without using any additional transistor. The other building blocks are also simplified for lower power consumption. This ADC occupies an area of 0.046 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . At 0.9 V and 1 kS/s, the 10-bits ADC consumes 5.8 nW, in which, 2.34 nW is contributed by leakage power consumption. The ADC achieves 9.1-ENOB and an energy efficiency of 10.94-fJ/conversion step.

A 0.6-V 8.3-ENOB asynchronous SAR ADC for biomedical applications

A microwatt asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is presented. The supply voltage of the SAR ADC is decreased to 0.6 V to fit the low voltage and low power requirements of biomedical systems. The tail capacitor of the DAC array is reused for least significant bit conversion to decrease the total DAC capacitance thus reducing the power. Asynchronous control logic avoids the high frequency clock generator and further reduces the power consumption. The prototype ADC is fabricated with a standard 0.18 μm CMOS technology. Experimental results show that it achieves an ENOB of 8.3 bit at a 300-kS/s sampling rate. Very low power consumption of 3.04 μW is achieved, resulting in a figure of merit of 32 fJ/conv.-step.

Design and analysis of high speed capacitive pipeline DACs

Design of a high speed capacitive digital-to-analog converter (SC DAC) is presented for 65 nm CMOS technology. SC pipeline architecture is used followed by an output driver. For GHz frequency operation with output voltage swing suitable for wireless applications (300 mVpp) the DAC performance is shown to be limited by the clock feed-through and settling effects in the SC array rather than by the capacitor mismatch or kT/C noise, which appear negligible in this application. While it is possible to design a highly linear output driver with HD3 < −70 dB and HD2 < −90 dB over 0.5–5 GHz band as we show, the maximum SFDR of the SC DAC is 45 dB with 8-bit resolution and Nyquist sampling of 3 GHz. The capacitor array is designed based on the DAC design area defined in terms of the switch size and unit capacitance value. A tradeoff between the DAC bandwidth and resolution accompanied by SFDR is demonstrated. High linearity of the output driver is attained by a combination of two techniques, the derivative superposition (DS) and resistive source degeneration. In simulations the complete DAC achieves SFDR of 45 dB with 8-bit resolution for signal bandwidth 1.36 GHz with Nyquist sampling. With 6-bit and 5.5 GHz bandwidth 33 dB SFDR is attained. The total power consumption of the SC DAC is 90 mW with 1.2 V supply and clock frequency of 3 GHz.

A Time-Based Pipelined ADC Using Both Voltage and Time Domain Information

In this paper, a Nyquist ADC with a time-based pipelined TDC is proposed. In the proposed ADC, the first pipeline stage incorporates both residue amplification and a V-T conversion with high accuracy, efficiently realized by a low gain amplifier with only 24 dB dc gain. Furthermore, adding to power efficiency, a hybrid time-domain pipeline stage based on simple charge pump and capacitor DAC in its backend stages is also proposed. Using the right combination of voltage and time domain information, the proposed ADC architecture benefits from improved resolution and power efficiency, with MSBs resolved in voltage domain and LSBs in time domain. The measured results of the prototype ADC implemented in a 0.13 μm CMOS demonstrate peak SNDR of 69.3 dB at 6.38 mW power and 70 MHz sampling frequency. The FOM based on peak SNDR is 38.2 fJ/conversion-step.

A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS

A 6-bit, 1-GS/s subranging analog-to-digital converter (ADC) implemented in 65-nm CMOS is developed. The same capacitor DACs (CDACs) are used to sample the analog signals, thereby eliminating the errors between the coarse and fine decisions that occur when two different samplers are used to capture the signal. Both decisions use the same comparators, and a digitally assisted calibration circuit compensates for the errors in the different threshold levels used for the two decisions. This calibration eliminates redundant comparators, and thus, reduces the area. Reference voltages generators, which are implemented using resistor ladders in conventional subranging ADCs, are eliminated thanks to the use of the CDACs together with interpolation in the comparators. This solves two problems related to the resistor ladder, namely, the trade-off between the settling time and the static-current consumption and signal dependent on-resistance of switches connected to intermediate potential nodes. A test chip fabricated in 65-nm CMOS technology operates at 1 GS/s with SNDR of 32.8 dB. Its active area is 0.044 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and its power consumption is 9.9 mW at a 1.1-V supply voltage.

Segmented Architecture for Successive Approximation Analog-to-Digital Converters

In this paper, the structure of a binary-weighted capacitive digital-to-analog converter (DAC) in a successive-approximation analog-to-digital converter (SA-ADC) is modified to a unary or segmented configuration to reduce the power consumption and improve the static linearity performance. In order to be able to choose the optimum value of the segmentation degree (i.e., the number of unary bits), the power consumption and the static linearity behavior of the segmented architecture as functions of the segmentation degree are analyzed. Circuit-level simulation results are presented to show the accuracy of the proposed equations. It is shown that for moderate and high-resolution ADCs, a segmentation degree of four or five bits is the optimum choice from the power-consumption viewpoint. Simulation results of a 1 V, 10-bit, 100-kS/s SA-ADC show that the power consumption of the entire capacitive DAC and the digital circuit of the segmented implementation with a segmentation degree of 4 is 30% less than the conventional design while the standard deviation of the differential nonlinearity is reduced by a factor of 2√(2).

High-linear, energy-efficient and area-efficient switching algorithm for high-speed SAR ADCs

Decreasing the size of DAC capacitors is a solution to achieve high-speed and low-power successive-approximation register analog-to-digital converters (SAR ADCs). But decreasing the size of capacitors directly effects the linearity performance of converter. In this paper, the effect of capacitor mismatch on linearity performance of charge redistribution SAR ADCs is studied. According to the achieved results from this investigation, a new tri-level switching algorithm is proposed to reduce the matching requirement for capacitors in SAR ADCs. The integral non-linearity (INL) and the differential non-linearity (DNL) of the proposed scheme are reduced by factor of two over the conventional SAR ADC which is the lowest compared to the previous schemes. In addition, the switching energy of the proposed scheme is reduced by 98.02% as compared with the conventional architecture which is the most energy-efficient algorithms in comparison with the previous algorithms, too. To evaluate the proposed method an 8-bit 50MS/s SAR ADC is designed in 0.18um CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 25-MHz input with 48.16dB SNDR while consuming about 589μW from a 1.2-V supply.

Analysis and Calibration of Nonbinary-Weighted Capacitive DAC for High-Resolution SAR ADCs

This brief analyzes the effect of capacitor variation on the design of high-resolution nonbinary-weighted successive-approximation-register analog-to-digital converters in terms of radix, conversion steps, and accuracy. Moreover, the limitation caused by the one-side redundancy of the nonbinary-weighted network is addressed and a corresponding solution with a mathematical derivation is provided. In order to relax the mismatch requirement on the capacitor sizing while still ensuring enough linearity, a bottom-up weight calibration technique accounting for noise and offset errors is proposed, and its effectiveness is demonstrated. This calibration approach can be easily incorporated into a charge-redistribution converter without modifying its main architecture and conversion sequence.

A Switch-Capacitor DAC Successive Approximation ADC Using Regulated Clocked Current Mirror

This paper presents a novel design of switch capacitor DAC successive approximation analog to digital converter (SAR-ADC) using regulated clocked current mirrors. The regulated clocked current mirror (RCCM) design is introduced to source (and sink) the constant current to (and from) the only capacitor in the circuit. The RCCM functions dynamically providing invariable current when required. Moreover when active, RCCM is capable of stabilizing the output current even in presence of voltage variations at its output. DC reference current from RCCM, charging or discharging the single capacitor in the circuit, is controlled by pulse width modulated signal to realize switch-capacitor DAC. Verilog-A script is written for switch control scheme to generate the control signals for RCCM. A dynamic latched comparator is employed to reduce the power consumption in circuit. An 8-bit SAR ADC that exhibits a maximum sampling frequency of 100 kHz is designed in 90 nm CMOS technology and its working is verified through circuit level simulations. This ADC achieves signal to noise and distortion ratio (SNDR) of 45.62 dB which corresponds to effective number of bits (ENOB) of 7.3 bits. At 1 V supply and 100 kS/s, power consumption in ADC is 6 μW while the calculated peak values of DNL and INL are +1.06/-0.40 LSB and +0.53/-1.33 LSB respectively. 

A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

An 8b 1.2 GS/s single-channel Successive Approximation Register (SAR) ADC is implemented in 32 nm CMOS, achieving 39.3 dB SNDR and a Figure-of-Merit (FoM) of 34 fJ per conversion step. High-speed operation is achieved by converting each sample with two alternate comparators clocked asynchronously and a redundant capacitive DAC with constant common mode to improve the accuracy of the comparator. A low-power, clocked capacitive reference buffer is used, and fractional reference voltages are provided to reduce the number of unit capacitors in the capacitive DAC (CDAC). The ADC stacks the CDAC with the reference capacitor to reduce the area and enhance the settling speed. Background calibration of comparator offset is implemented. The ADC consumes 3.1 mW from a 1 V supply and occupies 0.0015 mm2.

A 10b/12b 40 kS/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ/Conversion-Step

This paper presents a power-efficient 10/12 bit 40 kS/s SAR ADC for sensor applications. It supports resolutions of 10 and 12 bit and sample rates from DC up to 40 kS/s to accommodate a variety of sensor applications. A Data-Driven Noise-Reduction method is introduced to selectively enhance the comparator noise performance. In this way, a higher ADC resolution can be achieved with a small increase of the power consumption. A self-oscillating comparator is used to generate the bit-cycling clock internally. In this way, the ADC only requires an external clock at the sample-rate frequency. A segmented capacitive DAC with 250 aF unit elements is applied to save power and to reduce DNL errors at the same time. The implemented prototype in 65 nm CMOS occupies an area of 0.076 mm 2. For the two supported resolutions (10/12 bit), the ADC achieves an ENOB of 9.4 and 10.1 bit while consuming 72 and 97 nW from a 0.6 V supply at 40 kS/s. This leads to power efficiencies of 2.7 and 2.2 fJ/conversion-step for 10 bit and 12 bit resolution, respectively. Furthermore, the leakage power, which is below 0.4 nW, ensures that the efficiency can be maintained down to very low sample rates.

A Digital-Domain Calibration of Split-Capacitor DAC for a Differential SAR ADC Without Additional Analog Circuits

A digital-domain calibration method is proposed for a split-capacitor DAC (split-CDAC) used in a differential-type 11-bit SAR ADC. It calibrates the nonlinearities of SAR ADC due to the DAC capacitance mismatch as well as the two parasitic capacitances connected in parallel with each of the bridge capacitor and the LSB bank of split-CDAC. The proposed ADC does not require any additional analog circuits for calibration, because it utilizes one of the two split-CDACs to measure the error codes of the other split-CDAC. During the normal A/D conversion step, the 11.5-bit raw SAR code output of ADC is added to the pre-measured error codes to generate the 11-bit calibrated output code. The analog block of the ADC was fabricated in a 0.13- μm CMOS process, and the digital block was implemented in a FPGA. The measured SNDR and SFDR are 61.6 dB (ENOB 9.93 bits) and 78 dB at the Nyquist rate with a 5 kHz sine wave input. INL and DNL are measured to be +0.96/-0.98 LSB, and +0.96/-0.97 LSB, respectively. This work extends the prior work by utilizing an additional 0.5-bit raw SAR code to eliminate the missing code, and by employing a temporal averaging with a FIR LPF to measure the error code reliably in spite of the supply noise.

Design considerations of calibration DAC in self-calibrated SAR A/D converters

A capacitive calibration digital-to-analog converter (CDAC) is commonly used to reduce the mismatch-induced linearity errors for successive approximation register (SAR) analog-to-digital converters (ADC) employing capacitor arrays. There are complicated design considerations in determining the number of bits, the unit capacitor value and even the parasitic capacitors of the CDAC, as these factors affect or are determined by the achievable ADC resolution, the main DAC's capacitance, and the main DAC unit capacitance value, etc. This paper is the first to present a systematic analysis on these relationships. The analysis is validated by behavioral and circuit simulation results.

Design of low-power SAR ADCs using hybrid DACs

In the past decade, successive approximation register (SAR) analog-to-digital converter (ADC) has become a popular topology in a wide range of resolutions and sampling rates. This paper investigates methods to improve the energy-and-area efficiency of the SAR ADCs by focusing on the design of the internal digital-to-analog converter (DAC). Different hybrid resistive---capacitive DACs are studied in detail. It is shown that more than an order of magnitude improvement in energy efficiency of the DAC is achievable. The conditions for such an improvement are discussed.

An 8/10 bit 200/100MS/s configurable asynchronous SAR ADC

This paper presents an asynchronous 8/10 bit configurable successive approximation register analog-to-digital converter (ADC). The proposed ADC has two resolution modes and can work at a maximal sampling rate of 200 and 100MS/s for 8 bit mode and 10 bit mode respectively. The ADC uses a custom-designed 1 fF unit capacitor to reduce the power consumption and settling time of capacitive DAC, a dynamic comparator with tail current to minimize kickback noise and improve linearity. Moreover, asynchronous control technique is utilized to implement the ADC in a flexible and energy-efficient way. The proposed ADC is designed in 90 nm CMOS technology. At 100MS/s and 1.0 V supply, the ADC consumes 1.06 mW and offers an ENOB of 9.56 bit for 10 bit mode. When the ADC operates at 8 bit mode, the sampling rate is 200MS/s with 1.56 mW power consumption from 1.0 supply. The resulted ENOB is 7.84 bit. The FOMs for 10 bit mode at 100MS/s and 8 bit mode at 200MS/s are 14 and 34 fJ/conversion-step respectively.

An 88-dB Max-SFDR 12-bit SAR ADC With Speed-Enhanced ADEC and Dual Registers

A 12-bit 3-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) was implemented with a modified addition-only digital error correction (ADEC) and a dual-register-based DAC control as speed-enhancement techniques. The proposed speed-enhanced ADEC (SE-ADEC) scheme employs designated capacitors for redundancy-related DAC operation and thus eliminates MUX stages from the DAC control logic. Further speed enhancement is achieved by the dual-register structure that eliminates the entire DAC switching logic. The prototype ADC was fabricated in a 0.35- μm CMOS process utilizing only thick gate transistors with a minimum gate length of 0.5 μm. With a highly linear capacitor DAC design, the prototype ADC achieves 0.38 LSB INL without calibration. The measured spurious-free dynamic range and signal-to-noise and distortion ratio (SNDR) at a low-frequency operation of 250 kS/s are 88 and 68 dB, respectively. At a sample rate of 3 MS/s, the ADC achieves a peak SNDR of 64 dB with a total power dissipation of 1.23 mW under a 2.3-V supply. The FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Nyq</sub> is a 368-fJ/conversion-step.

Adaptive successive approximation ADC for biomedical acquisition system

This work proposes a low-power adaptive successive approximation ADC that operates in 12-bit and 8-bit resolution for data acquisition in biomedical system. A fully differential architecture and an energy-efficient switching scheme are employed. The modified switching operation allows the output voltage of the DAC capacitor array to approach the common mode voltage in order to reduce the offset voltage variation of the comparator. A test chip is implemented using a 0.18-µm CMOS process. The core area is 904×650μm2 The measurement results show that performance integrity and power efficiency are both significantly achieved in 12-bit resolution only. After the test using 1.8-V supply voltage, the SNDR is 65.59dB and ENOB is 10.62 bits. Using 200kS/s sampling rate, the ADC core consumption is 40.24μW and 18.63μW, for 12-bit and 8-bit case, respectively.

Implementation of a digital trim scheme for SAR ADCs

Abstract. Successive approximation register (SAR) analog-to-digital Converters (ADC) are based on a capacitive digital-to-analog converter (CDAC) (McCreary and Gray, 1975). The capacitor mismatch in the capacitor array of the CDAC impacts the differential non-linearity (DNL) of the ADC directly. In order to achieve a transfer function without missing codes, trimming of the capacitor array becomes necessary for SAR ADCs with a resolution of more than 12 bit. This article introduces a novel digital approach for trimming. DNL measurements of an 18 bit SAR ADC show that digital trimming allows the same performance as analog trimming. Digital trimming however reduces the power consumption of the ADC, the die size and the required time for the production test.

A 10-bit CMOS Capacitive and Resistive D/A Converter Integrated with Self-adjusted Reference Circuit

A 10-bit, digital-to-analog converter (DAC) for static/dc operation is fabricated in a standard 0.5 ¼ complementary metal oxide semiconductor (CMOS) process. The DAC is optimized for system-on-chip (SOC) readout circuits. A capacitive and resistive DAC is adopted for the DAC core to obtain area reduced and good monotony. A self-adjusted reference circuit is proposed in order to provide differential reference voltages for getting better accuracy. A unique common centroid layout is used in the capacitor network to reduce the effect of thermal or process linear gradients. The measured results of our work with integral non-linearity (INL) and differential non-linearity (DNL) are less than 0.54 LSB and 0.43 LSB, respectively. The power consumption is about 16 mW.