Capacitive DAC Research Articles

A 4.06 mW 10-bit 150 MS/s SAR ADC With 1.5-bit/cycle Operation for Medical Imaging Applications

This paper reports a 10-bit 150 MS/s successive approximation register analog-to-digital converter with binary-scaled redundancy-facilitated error correction technique. The proposed 1.5-bit/cycle technique with built-in capacitive digital-to-analog converter (CDAC) redundancy, corrects multiple erroneous decisions in a total of nine conversion cycles. The proposed binary-scaled redundancy provides a 12.5% error tolerance range for the incomplete CDAC voltage settling. The digital error-correction logic circuit presented uses a bit-overlap-and-add technique. The prototype chip was fabricated in 65-nm CMOS technology and occupies chip area of 0.038 mm2. It consumes 4.06 mW from a 1.2 V supply, achieving the Nyquist signal-to-noise-and-distortion ratio of 57.81 dB and the effective number of bits of 9.31-bit at an operating frequency of 150 MS/s, corresponding to the figure-of-merit of 42.6 fJ/ conversion-step.

A Nyquist Rate SAR ADC Employing Incremental Sigma Delta DAC Achieving Peak SFDR = 107 dB at 80 kS/s

This paper introduces an architecture and design for high-resolution high-linearity Nyquist rate successive approximation register (SAR) analog-to-digital converters (ADCs) using a hybrid capacitive and incremental $\Sigma \Delta $ digital-to-analog converter (DAC). The proposed architecture benefits from an intrinsically linear 1.5-bit $\Sigma \Delta $ DAC to resolve the fine bits of the SAR ADC after a coarse conversion phase with a monotonically switched capacitive DAC (CDAC). The achieved linearity relies neither on a highly matched CDAC nor on any dynamic linearization techniques but on a single calibration of the coarse CDAC using the available $\Sigma \Delta $ DAC at startup. Therefore, the CDAC can be sized solely upon noise requirements. The SAR ADC employs two parallel dynamic comparators for improved power efficiency. A prototype was fabricated in a 40-nm CMOS, with power supplies of 1.1 and 2.5 V. It occupies an active area of only 0.074 mm2. The prototype achieves a measured peak spurious free dynamic range (SFDR) of 107 dB and peak signal to noise and distortion ratio (SNDR) of 84.8 dB dB at 80-kS/s Nyquist rate operation with 5.3-kHz input. The measured performance at the Nyquist frequency, limited by signal source quality, is SFDR = 99.5 dB and SNDR = 83.5 dB. The core power consumption is 110 $\mu \text{W}$ . In oversampling mode, the ADC achieves an SNDR above 90 dB over a 5-kHz bandwidth.

Nano-Watt Class Energy-Efficient Capacitive Sensor Interface With On-Chip Temperature Drift Compensation

This paper presents a nano-watt class energyefficient capacitive sensor interface with on-chip temperature compensation. To achieve both high resolution and sensing accuracies, we exploit the fundamental limits of a two-step incremental-ADC and present a systematic study on the optimal coarse/fine bit allocations in the presence of mismatch errors. Efficient hardware reuse is ensured by utilizing the same loop filter, capacitive DAC, and digital controller in coarse/fine conversions for both capacitance and temperature readouts. A reconfigurable pre-gain stage for both capacitance and temperature sensing and a block-based data weighted averaging scheme are also employed to improve the overall system efficiency with 60% control overhead reduction. Optimized biasing circuit and subthreshold-biased amplifier with indirect compensation are utilized to achieve high accuracy with nano-watt power. Fabricated in a standard 0.18-μm CMOS process, the chip prototype consumes only 570 nW and achieves measured capacitance and temperature sensing inaccuracies of ±0.17 fF (1σ) from 0 to 10.8 pF and ±0.18 °C (3σ) from 0 to 100 °C, respectively. System level verification with a commercial MEMS pressure sensor shows a measured pressure sensing error improvement of >150× after temperature compensation.

A 14-bit 10kS/s power efficient 65nm SAR ADC for cardiac implantable medical devices

This brief presents a 10kS/s 14 bit 12.5 ENOB Successive Approximation Register Analog-to- Digital Converter for Cardiac Implantable Medical. For achieving power efficient operation, SAR ADC employ SAR control, a new power and noise efficient comparator topology, non- binary weighted capacitive DAC. The linearity of implemented SAR ADC is enhanced with the uniform geometry of non-binary weighted capacitive DAC.The proposed SAR ADC is implemented using 65nm CMOS technology. The latched comparator consumes a power of 2.4uW and it provides an ENOB of 12.6 at a supply voltage of 1V.The INL is between -2.7/+1.6 LSB and DNL is between -0.6/+1.4LSB. The FOM of ADC is 40fJ/conv. Step which is comparable with existing ADC topologies.

A 10-bit 300 MS/s 5.8 mW SAR ADC With Two-Stage Interpolation for PET Imaging

In this paper, a high speed low power 2b/cycle successive approximation register (SAR) analog-to-digital converter (ADC) is proposed for medical imaging. The ADC adopts a two-stage differential pair based interpolation technique that can reduce resolution of the capacitive DAC and avoid usage of smaller unit capacitor. A meta-stability immunity technique is proposed to enhance the asynchronous conversion. A design example of 10-bit 2b/cycle SAR ADC with sampling rate up to 300 MS/s is fabricated. Dissipating 5.8 mW with 1.2 V supply and occupying an active area of 0.082 mm2, the measured SFDR and SNDR at Nyquist input are 59-dB and 51.5-dB respectively. It achieves an effective resolution bandwidth of 360 MHz and a figure-of-merit of 61fJ/conversion-step.

A 10bit 20 kS/s 17.7 nW 9.1ENOB reference-insensitive SAR ADC in 0.18 μm CMOS

This paper presents a 10bit 20 kS/s 9.1ENOB SAR ADC employing an energy-efficient and highly-linear capacitor switching strategy in 0.18 μm CMOS process. The SAR ADC with this proposed strategy features better linearity due to the use of a relatively lower assistant reference, the value of which is equivalent to a quarter of the input swing. In addition, the accuracy of the assistant reference has no impact on the ADC performance, since only this assistant reference will be involved with the capacitive DACs during the conversion period. The ADC is powered by the supplies of 0.6 V/0.15 V. The capacitive DACs are supplied by the 0.15 V assistant reference, while the other blocks are powered by the 0.6 V reference. In this case, the ADC consumes 11.7 nW overall, resulting in a figure-of-merit (FOM) of 1.6fJ/conversion-step. At a 20-kS/s output rate, the measured results show the proposed SAR ADC performs a peak signal-to-noise-and-distortion ratio (SNDR) of 56.5 dB, a peak spurious-free-dynamic-range (SFDR) of 66.7 dB. The core area of the designed ADC is and 370 × 310 μm2.

A low-cost digital-domain foreground calibration for high resolution SAR ADCs

A digital-domain foreground calibration method simultaneously correcting mismatch errors in main capacitive digital to analog converter (CDAC) and “segment error” between main CDAC and sub-CDAC of split-CDAC array in high resolution successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. The actual weight is obtained with the digital-domain weight estimation algorithm. This proposed digital-domain calibration saves silicon area by eliminating the need for a dedicated calibration DAC employed in conventional CDAC mismatch calibration schemes. Behavioral simulation shows the proposed calibration is capable of correcting mismatch errors and “segment error” of split-CDAC array, and improving SNDR from 67.3 dB to 92.8 dB in a prototype 16 bit split-CDAC SAR ADC.

A 700-MS/s 6-bit SAR ADC with partially active reference voltage buffer

This paper presents a 700-MS/s 6-bit SAR ADC with a novel on-chip reference voltage buffer in a 40-nm CMOS Low-Leakage (LL) process. The reference voltage buffer is partially active depending on the operation state of the SAR ADC. The large driving current is provided only when the Capacitive Digital-to-Analog Converter (CDAC) is settling. This approach achieves 42% power reduction for the reference voltage buffer, which helps to improve the Figure-of-Merit (FoM) of the total SAR ADC chip. The measurement results show the ADC achieves an SNDR of 35.5 dB at the input frequency of 318.8 MHz. The chip consumes 4.0 mW including the SAR ADC core and the reference voltage buffer, resulting in an FoM of 117.8 fJ/conv.-step.

A 4.5 nV/√Hz Capacitively Coupled Continuous-Time Sigma-Delta Modulator with an Energy-Efficient Chopping Scheme

When chopping is applied to a continuous-time sigma-delta modulator (CT ${\Sigma \Delta }\text{M}$ ), quantization noise fold-back often occurs, leading to increased in-band noise. This can be prevented by employing a return-to-zero (RZ) digital-to-analog converter (RZ DAC) in the modulator’s feedback path and arranging the chopping transitions to coincide with its RZ phases. In this letter, this technique has been extended and implemented in an energy-efficient CT ${\Sigma \Delta }\text{M}$ intended for the readout of Wheatstone bridge sensors. To achieve a wide common-mode input range, the modulator’s summing node is implemented as an embedded capacitively coupled instrumentation amplifier which can be readily combined with a highly linear 1-bit capacitive RZ DAC. Measurements show that the proposed chopping scheme does not suffer from quantization noise fold-back and also allows a flexible choice of chopping frequency. When chopped at one-tenth of the sampling frequency, the modulator achieves 15 ppm INL, 4.5 nV/ ${\surd }$ Hz input-referred noise and a state-of-the-art noise efficiency factor of 6.1.

Analyses of parasitic capacitance effects and flicker noise of the DAC capacitor array for high resolution SAR ADCs

This paper analyses the effects of parasitic capacitances of unit capacitors on the accuracy and the noise performance of the DAC capacitor array in a SAR ADC, showing that thermal noise of the array decreases while gain error is introduced. The gain error is almost independent of the number of bits, but the dynamic range of the high resolution ADC is severely reduced due to the gain error. The post-layout parasitic capacitance analysis of a 10-bit poly-poly array shows a large difference between the top-plate and bottom-plate parasitic capacitances so that the gain error can be decreased by 152 times when top-plates are connected together as the output node of the array. The switching transistors' flicker noise calculation for a 10-bit and an 18-bit SAR ADC shows that flicker noise can be safely ignored for 10-bit 1MSPS SAR, but should be considered for the higher resolution SAR ADCs.

Analyses of parasitic capacitance effects and flicker noise of the DAC capacitor array for high resolution SAR ADCs

This paper analyses the effects of parasitic capacitances of unit capacitors on the accuracy and the noise performance of the DAC capacitor array in a SAR ADC, showing that thermal noise of the array decreases while gain error is introduced. The gain error is almost independent of the number of bits, but the dynamic range of the high resolution ADC is severely reduced due to the gain error. The post-layout parasitic capacitance analysis of a 10-bit poly-poly array shows a large difference between the top-plate and bottom-plate parasitic capacitances so that the gain error can be decreased by 152 times when top-plates are connected together as the output node of the array. The switching transistors' flicker noise calculation for a 10-bit and an 18-bit SAR ADC shows that flicker noise can be safely ignored for 10-bit 1MSPS SAR, but should be considered for the higher resolution SAR ADCs.

Energy-efficient Spread Second Capacitor Capacitive DAC for SAR ADC

An energy-efficient capacitive-digital-to-analog converter (C-DAC) switching with low common-mode voltage variation switching method is proposed for successive approximation register analog-to-digital converters (SAR ADCs). In the proposed spread second capacitor capacitive-DAC (SSC C-DAC), a role of capacitor for second conversion step is spread to all capacitors except the most significant bit (MSB) capacitor. The proposed SSC C-DAC achieves 98.1% more efficient switching energy and can be comprised of the number of quarter unit capacitor compared with conventional scheme. Furthermore, in order to achieve low variation of common-mode voltage, the proposed switching method adopts only one side of tri-state switching method in differential-type SAR ADC after second conversion.

A 10-bit 1 MS/s segmented Dual-Sampling SAR ADC with reduced switching energy

This paper implements a 10-bit segmented Dual-Sampling SAR ADC for a WPT system. To solve the mid-code problem of the Dual-Sampling structure and improve the linearity, a segmented structure is adopted in capacitive DAC. A new switching scheme is proposed for MSBs decisions to skip some of the unnecessary switching steps. This ADC is applied to digitize analog inputs of the different sub-blocks of the WPT system. Applying these techniques reduces the unit capacitor size, as well as the power consumption while improving the linearity of the system. The overall system achieves 9.8 ENOB at 1 MS/s conversion speed and consumes 19.6 μA from 3 V supply voltage. DNL and INL for this structure are measured to be −0.63–0.56 and −0.85–0.79 LSB respectively. The active area of the ADC in 0.18 μm CMOS process is 760 × 430 μm2.

A 0.8–1.2 V 10–50 MS/s 13-bit Subranging Pipelined-SAR ADC Using a Temperature-Insensitive Time-Based Amplifier

This paper presents an energy-efficient 13-bit 10–50 MS/s subranging pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) with power supply scaling. In the presented ADC, an SAR-assisted subranging floating capacitive DAC switching algorithm reduces switching energy along with enhanced linearity and speed in the first-stage SAR ADC. A following temperature-insensitive time-based residue amplifier realizes open-loop residual amplification without background calibration, while maintaining the benefits of dynamic operation and noise filtering. Furthermore, asynchronous SAR control logic employs a pre-window technique to accelerate SAR logic operations. The prototype ADC was fabricated in a 130-nm CMOS process with an active area of 0.22 mm2. With a 1.2-V power supply and a Nyquist frequency input, the ADC consumes 1.32 mW at 50 MS/s and achieves signal-to-noise and distortion ratio and spurious-free dynamic range of 69.1 and 80.7 dB, respectively. The operating speed is scalable from 10 to 50 MS/s with a scalable power supply range of 0.8–1.2 V. Walden FoMs of 4–11.3 fJ/conversion-step are achieved.

Use DAS algorithm to break through the device limitations of switched-capacitor-based DAC in an ADC consisting of pipelined SAR and TDC

Switched capacitors are widely used in integrated circuits for discrete-time signal processing. Metal-Insulator-Metal (MIM) capacitors and MOSFET switches are commonly used for switched-capacitor circuits. They impose limitations in the power consumption and the bandwidth of the circuits. For instance, the switched-capacitor digital-to-analog converter (DAC) is the critical circuit block that determines the performance in a successive approximation register (SAR) analog-to-digital converters (ADC). In this paper, a design using the detect-and-skip (DAS) algorithm to break through the device limitations of switched-capacitor-based DACs is analyzed in a coarse-fine SAR ADC architecture. When it is shown that compared with the state-of-the-art Vcm-based capacitive DAC (CDAC), the DAS algorithm reduces 55% of the energy and extends the valid bandwidth from 2 MHz to 16 MHz with a 6-bit resolution under the same setting and technology. Besides, a time-to-digital converter (TDC)-assisted pipelined SAR ADC architecture using the DAS algorithm is proposed. Implemented in a 180 nm CMOS process, the 10-bit 10-MS/s prototype measures an energy efficiency of 57.8 fJ/conv.-step.

An 8 bit 1 MS/s SAR ADC with 7.72-ENOB**Project supported by the National Natural Science Foundation of China (Nos. 61161003, 61264001, 61166004) and the Guangxi Key Laboratory of Precision Navigation Technology and Application Foundation (No. DH201501).

This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with output offset voltage storage technology is used to improve the precision. Adding an extra positive feedback in the latch is to increase the speed. What is more, two pairs of CMOS switches are utilized to eliminate the kickback noise introduced by the latch. The proposed SAR ADC was fabricated in SMIC CMOS technology. The measured results show that this design achieves an SFDR of 61.8 dB and an ENOB of 7.72 bits, and it consumes 67.5 μW with the FOM of 312 fJ/conversion-step at 1 MS/s sample under 1.8 V power supply.

A 5-GS/s 10-b 76-mW Time-Interleaved SAR ADC in 28 nm CMOS

This paper presents a 5-GS/s 12-way 10-b time-interleaved successive approximation register (SAR) ADC for direct sampling receivers. Proper signal and clock distribution along the multiple channels are utilized to mitigate interchannel bandwidth and timing mismatches. A digitally assisted calibration is introduced to remove the interchannel offset, gain, and timing mismatch. The T-type bootstrapped sampling switches minimize the interchannel crosstalk among top-plate sampling SAR channels and the signal-dependent leakage current during SAR conversion cycles. The power efficiency of this ADC is significantly improved by many design techniques. The merged capacitor switching algorithm leads to high switching efficiency and a smaller area. The modified reference voltage scheme optimizes input common-mode voltage of the comparators. The optimal subradix-2 capacitive DAC results in low-power reference buffers and higher conversion speed. This ADC achieves 49-dB SNR, 52-dB THD, and 42-dB SNDR up to Nyquist frequency at 5 GS/s, consumes 76 mW from 1 V supply, and occupies 0.57 mm $^{{ {2}}}$ in 28 nm CMOS technology. The implemented architecture also demonstrates high scalability to advanced CMOS technology nodes and has even higher power efficiency potential.

A Nonlinear Switched State-Space Model for Capacitive RF DACs

This paper presents a nonlinear state-space model (SSM) for a low power 28-nm complementary metal–oxide–semiconductor switched-capacitor digital-to-analog converter. The proposed model utilizes current–voltage (I-V) input and output relationships for passive devices, which are described by a set of first-order differential equations. The proposed model significantly increases accuracy when compared with the state-of-the-art models. The SSM simulation results have been verified using SpectreRF transistor-level simulations and validated by on-chip measurements.

A hybrid DAC switching technique for SAR ADCs

In recent years, the area of Wireless Sensor Networks has seen a tremendous growth and is instrumental in a multitude of applications ranging from health monitoring to geo fencing. Analog-to-Digital Converters (ADCs) are vital to any low-cost, energy-efficient sensor node in that they convert the sensed signal into its digital counterpart, which is then used processed by the digital circuitry. In this paper, a Capacitive Digital-to-Analog Converter (CDAC) switching technique is proposed that is aimed toward the design of an energy-efficient ADC. The presented switching technique is $$97.85\%$$97.85% more energy-efficient than the traditional CDAC architecture. Besides its energy efficiency, the technique reduces the overall size of the CDAC and its settling time. Theoretical analysis has been presented along with detailed simulation results as a proof of concept.

Low Power Design of a 1 V 8-bit 125 fJ Asynchronous SAR ADC with Binary Weighted Capacitive DAC

The work proposes an improved technique to design a low power 8-bit asynchronous successive approximation register (ASAR), an analog-to-digital converter (ADC). The proposed ASAR ADC consists of a comparator, ASAR (digital control logic block), and a capacitive-digital-to-analog convertor (C-DAC). The comparator is a preamplier-based improved positive feedback latch circuit which has a built-in sample and hold (S/H) functionality and saves an enormous amount of power. The implemented digital control logic block performing the successive approximation (SA) algorithm is totally unrestrained of the external clock pulse. The outputs from the comparator are given to a XOR logic whose outputs serve as an internally generated clock (ready signal) to trigger the digital control block. Hence, an external clock is not required to initiate the digital control block making its operation asynchronous. By implementing this, the ADC can circumvent the usage of an oversampled clock and can operate on a single low-speed sample clock. This, in turn, saves power and it cuts down the required resilience in sampling rates. The proposed ADC has been designed and simulated using UMC-0.18[Formula: see text][Formula: see text]m CMOS technology which dissipates 32.18[Formula: see text][Formula: see text]W power when operated on a single 1[Formula: see text]V power supply and achieves complete 8-bit conversion in 1.09[Formula: see text][Formula: see text]s. The relative accuracy of capacitor ratio, aperture jitter and FOM are 0.39[Formula: see text], 1.2[Formula: see text]ns and 125[Formula: see text]fJ/conversion-step, respectively.