Abstract
This paper analyses the effects of parasitic capacitances of unit capacitors on the accuracy and the noise performance of the DAC capacitor array in a SAR ADC, showing that thermal noise of the array decreases while gain error is introduced. The gain error is almost independent of the number of bits, but the dynamic range of the high resolution ADC is severely reduced due to the gain error. The post-layout parasitic capacitance analysis of a 10-bit poly-poly array shows a large difference between the top-plate and bottom-plate parasitic capacitances so that the gain error can be decreased by 152 times when top-plates are connected together as the output node of the array. The switching transistors' flicker noise calculation for a 10-bit and an 18-bit SAR ADC shows that flicker noise can be safely ignored for 10-bit 1MSPS SAR, but should be considered for the higher resolution SAR ADCs.
Highlights
The successive approximation register (SAR) ADC has been reported as the lowest power consuming ADC [1] which is useful in low-power, low data rate biomedical applications
The accuracy parameters of the binary-weighted Digital-analog Converter (DAC) capacitor array considered in literature are the matching error only [8] and both of the matching error and thermal noise [9], which are adequate to accuracy calculations since parasitic effects are generally relatively low
Parasitic capacitances have both sides of effects on the DAC capacitor array
Summary
The successive approximation register (SAR) ADC has been reported as the lowest power consuming ADC [1] which is useful in low-power, low data rate biomedical applications (such as acquisition of physiological signals of ECG, EEG [2, 3] and biometric signal of fingerprint [4], human-computer interface [5] and eye gaze tracking [6]). The absolute accuracy of the capacitor value in the DAC capacitor array is relatively poor in a CMOS process. Special layout techniques, such as the common centroid one [7], are commonly employed for the implementation of the binary-weighted DAC capacitor array in order to achieve the required accuracy. As the measurement accuracy increases, there is another concern of whether flicker noise produced by switching transistors in the DAC capacitor array is small enough to be neglected in the high resolution SAR ADC design, because flicker noise of switching transistors in charging branches increases as a result of the increasing bandwidth of the SAR ADCs when the number of bits increased [13]. The bandwidth of the SAR ADC is estimated to evaluate the general figure of flicker noise, showing that for a high resolution SAR ADC design flicker noise of switching transistors should not be ignored
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