A 10bit 20 kS/s 17.7 nW 9.1ENOB reference-insensitive SAR ADC in 0.18 μm CMOS

Abstract

This paper presents a 10bit 20 kS/s 9.1ENOB SAR ADC employing an energy-efficient and highly-linear capacitor switching strategy in 0.18 μm CMOS process. The SAR ADC with this proposed strategy features better linearity due to the use of a relatively lower assistant reference, the value of which is equivalent to a quarter of the input swing. In addition, the accuracy of the assistant reference has no impact on the ADC performance, since only this assistant reference will be involved with the capacitive DACs during the conversion period. The ADC is powered by the supplies of 0.6 V/0.15 V. The capacitive DACs are supplied by the 0.15 V assistant reference, while the other blocks are powered by the 0.6 V reference. In this case, the ADC consumes 11.7 nW overall, resulting in a figure-of-merit (FOM) of 1.6fJ/conversion-step. At a 20-kS/s output rate, the measured results show the proposed SAR ADC performs a peak signal-to-noise-and-distortion ratio (SNDR) of 56.5 dB, a peak spurious-free-dynamic-range (SFDR) of 66.7 dB. The core area of the designed ADC is and 370 × 310 μm2.