A SAR ADC for multichannel synchronous signal acquisition

Abstract

A synchronous sampling multichannel ADC is proposed to sample several signals at the same time and digitize the sampled signals in sequence. Instead of using multiple ADCs or multiple samplers, a modified SAR ADC with multiple capacitive DACs is applied to largely save area and reduce gain and offset mismatches between channels. A common-mode voltage resampling technique is proposed to reduce crosstalk errors between the multiple input signals below the ADC noise floor. To verify the ADC structure, a 10-bit 4-channel SAR ADC has been prototyped and implemented with a 180-nm CMOS technology. The ADC area is 0.325 mm2 (without PAD). At the sampling frequency of 250 kHz per channel, it uses 62 μW to achieve 9.38 ENOB for four input signals. The resolutions of the four channels are mainly limited by the DAC performances.