Abstract
In order to realize the acquisition and storage of underwater acoustic signals for aiming at the requirements of multi-channel, low power consumption and small volume for underwater receiver extension of sonar system, a multi-channel signal acquisition and storage system based on FPGA and STM32 with variable number of working channels and sampling frequency is designed, in which the system is consisted of 8 pieces, 8 channel and 24 bits high dynamic range Δ-Σ ADS1278 ADC chip to synchronous multi-channel analog signal acquisition. FPGA, as the acquisition sequence and logic control, reads and collates the ADC chip data and writes it into the internal high-capacity FIFO, and adds corresponding operations according to the characteristics of FIFO in an application. SMT32 single-chip microcomputer reads the FIFO data through the high-speed SPI interface with FPGA and writes the multi-channel data into the high-capacity SD card. The testing results have verified that the system has characteristics such as stable and reliable, easy configuration, low power consumption, can guarantee the multichannel data serial transmission, storage, accurate, up to 64 analog signals at the same time the real-time collection and storage, top 20 kHz sampling rate, the system total power of the system of about 3W, data rates up to 100 Mb/s, fully meet the needs of underwater sound acquisition system.
Highlights
a multi⁃channel signal acquisition and storage system based on FPGA
in which the system is consisted of 8 pieces
adds corresponding operations according to the characteristics of FIFO
Summary
摘 要:为了实现对水声信号的采集与存储,并针对声呐系统水下接收系统对多通道、高精度、低功 耗、小体积的技术要求,设计了一种基于 FPGA 和 STM32 的工作通道数量和采样频率可变的多通道信 号采集存储系统。 该系统采用 8 块 8 通道 24 bit 高动态范围的 Δ⁃Σ 型 ADC 芯片 ADS1278 对多路模 拟信号进行同步采集. 另外根据数据手册可以使 A / D 模块中工作时 钟 CLK 与数据输出时钟 SCLK 共用同一个时钟信 号,8 个 A / D 模块共用同步信号( SYNC) 。 这样的 设计在满足系统正常工作的情况下,占用 I / O 端口 数量少,减少硬件连接的复杂程度。 A / D 与 FPGA 连接方式如图 3 所示。
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More From: Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University
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