Abstract
A New Shift Monotonic Switching (NSMS) DAC capacitor array switching scheme suitable for successive approximation register Analog-to-Digital Converters (SAR ADCs) is proposed. The proposed DAC switching scheme utilizes two DAC arrays to achieve double-swing input signals without increasing the size of the capacitor array. In this paper, a 10-bit SAR ADC behavioral-level model is established through detailed analysis of the previously proposed energy-efficient DAC capacitor array switching scheme and the proposed NSMS switching scheme. Compared to the merged capacitor switching (MCS) scheme, the proposed NSMS switching scheme achieves an average switching energy optimization of 88% while maintaining better linearity. Additionally, for low-sampling-frequency applications, an improved SAR ADC architecture based on the NSMS capacitor array switching scheme is provided, which further reduces power consumption and system overhead.
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