Time Assisted SAR ADC with Bit-guess and Digital Error Correction

Abstract

This work presents an original SAR ADC architecture for low-power ADC applications. The proposed architecture uses a Time-to-Digital converter (TDC) to apply a window switching scheme in the SAR algorithm that predicts the switching value of the three MSB CDAC capacitors in just one SAR cycle. The switching scheme also implements a correlated-reversed switching (CRS), improving the converter linearity. The proposed archi-tecture is demonstrated on a 10-bit SAR ADC implementation, which takes ten SAR cycles to provide a l2-bit word to a digital error correction (DEC) block that translates it into a final 10-bit digital output. Considering a Gaussian random distribution to model the variability of unit capacitances, MATLAB simulations demonstrate an ADC linearity that achieves 52% of DNL and 69% of INL values of a conventional VCM-based switching method. The switching scheme reduces by 50% the average switching energy compared with the conventional VCM-based switching method, considering a design with the redundancy searching range of the implemented CDAC. The proposed SAR ADC architecture is designed and simulated in a 28nm CMOS technology. The proposed architecture, working with a 600mV power supply with 10MHz sample frequency, demonstrates an improvement of 28% in the ADC power dissipation compared with a 10-bit SAR ADC with traditional implementation designed to have the same linearity.